There seems to be some confusion...perhaps mine? "volatile" as someone so excellently put, means "don't trust the cached value, reread it". "memory barriers" are addressed in, as always, Rubini and Corbet at http://www.xml.com/ldd/chapter/book/ch08.html#t1 I believe the point here is that as programmers we write code, especially a series of register reads/writes to our hardware. It may be important that, and we are expecting, these register accesses to arrive in the order in which we originally wrote them. However, compilers may "optimize" these writes into a different order. This may make no difference to the hardware. On the other hand, it may be disastrous for said accesses to arrive in a different order than that which was indicated when we wrote the code. Needless to say, bugs arising from register accesses arriveing "out of order" are...difficult...to track down. <snip> #include <linux/kernel.h> void barrier(void) This function tells the compiler to insert a memory barrier, but has no effect on the hardware. Compiled code will store to memory all values that are currently modified and resident in CPU registers, and will reread them later when they are needed. #include <asm/system.h> void rmb(void); void wmb(void); void mb(void); These functions insert hardware memory barriers in the compiled instruction flow; their actual instantiation is platform dependent. An rmb (read memory barrier) guarantees that any reads appearing before the barrier are completed prior to the execution of any subsequent read. wmb guarantees ordering in write operations, and the mb instruction guarantees both. Each of these functions is a superset of barrier. A typical usage of memory barriers in a device driver may have this sort of form: writel(dev->registers.addr, io_destination_address); writel(dev->registers.size, io_size); writel(dev->registers.operation, DEV_READ); wmb(); writel(dev->registers.control, DEV_GO); In this case, it is important to be sure that all of the device registers controlling a particular operation have been properly set prior to telling it to begin. The memory barrier will enforce the completion of the writes in the necessary order. </snip> Harmony, --Christine __________________________________________________ Do You Yahoo!? Yahoo! Finance - Get real-time stock quotes http://finance.yahoo.com -- Kernelnewbies: Help each other learn about the Linux kernel. Archive: http://mail.nl.linux.org/kernelnewbies/ FAQ: http://kernelnewbies.org/faq/
