I recently read the discussion on lkml about cache aligning data structures used for DMA on non-coherent machines. I have a couple PowerMac 6500s which are affected by this issue. For any ethernet card I put in these machines, I have to modify the drivers to use cache aligned descriptors in some fashion. The current approach I tried after reading the lkml discussion is to create a pci pool (aligned to L1_CACHE_BYTES) and allocate each descriptor from this pool. Is this something that should be done for every descriptor ring based driver to ensure portabiliy? Or can anyone suggest a better approach, or is there a good reason this is not done now? It seems useful to me as Linux makes further progress in embedded systems. --------------------------------------------------------------------------- | Nathan Ingersoll | Computer Science/Mathematics | | mailto: ningerso@d.umn.edu | University of Minnesota-Duluth | | http://umn.edu/~ningerso | http://www.d.umn.edu | --------------------------------------------------------------------------- -- Kernelnewbies: Help each other learn about the Linux kernel. Archive: http://mail.nl.linux.org/kernelnewbies/ FAQ: http://kernelnewbies.org/faq/
