The patch titled drivers/gpu/drm/i915/intel_display.c: disable SR when more than one pipe is enabled has been added to the -mm tree. Its filename is drivers-gpu-drm-i915-intel_displayc-disable-sr-when-more-than-one-pipe-is-enabled.patch Before you just go and hit "reply", please: a) Consider who else should be cc'ed b) Prefer to cc a suitable mailing list as well c) Ideally: find the original patch on the mailing list and do a reply-to-all to that, adding suitable additional cc's *** Remember to use Documentation/SubmitChecklist when testing your code *** See http://userweb.kernel.org/~akpm/stuff/added-to-mm.txt to find out what to do about this The current -mm tree may be found at http://userweb.kernel.org/~akpm/mmotm/ ------------------------------------------------------ Subject: drivers/gpu/drm/i915/intel_display.c: disable SR when more than one pipe is enabled From: David John <davidjon@xxxxxxxxxxx> Self Refresh should be disabled on dual plane configs. Otherwise, as the SR watermark is not calculated for such configs, switching to non VGA mode causes FIFO underrun and display flicker. Addresses http://bugzilla.kernel.org/show_bug.cgi?id=14897 Signed-off-by: David John <davidjon@xxxxxxxxxxx> Acked-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx> Cc: Eric Anholt <eric@xxxxxxxxxx> Cc: Dave Airlie <airlied@xxxxxxxx> Cc: <stable@xxxxxxxxxx> Signed-off-by: Andrew Morton <akpm@xxxxxxxxxxxxxxxxxxxx> --- drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff -puN drivers/gpu/drm/i915/intel_display.c~drivers-gpu-drm-i915-intel_displayc-disable-sr-when-more-than-one-pipe-is-enabled drivers/gpu/drm/i915/intel_display.c --- a/drivers/gpu/drm/i915/intel_display.c~drivers-gpu-drm-i915-intel_displayc-disable-sr-when-more-than-one-pipe-is-enabled +++ a/drivers/gpu/drm/i915/intel_display.c @@ -2622,6 +2622,10 @@ static void g4x_update_wm(struct drm_dev sr_entries = roundup(sr_entries / cacheline_size, 1); DRM_DEBUG("self-refresh entries: %d\n", sr_entries); I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); + } else { + /* Turn off self refresh if both pipes are enabled */ + I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) + & ~FW_BLC_SELF_EN); } DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n", @@ -2665,6 +2669,10 @@ static void i965_update_wm(struct drm_de srwm = 1; srwm &= 0x3f; I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); + } else { + /* Turn off self refresh if both pipes are enabled */ + I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) + & ~FW_BLC_SELF_EN); } DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", @@ -2733,6 +2741,10 @@ static void i9xx_update_wm(struct drm_de if (srwm < 0) srwm = 1; I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f)); + } else { + /* Turn off self refresh if both pipes are enabled */ + I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) + & ~FW_BLC_SELF_EN); } DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", _ Patches currently in -mm which might be from davidjon@xxxxxxxxxxx are drivers-gpu-drm-i915-intel_displayc-disable-sr-when-more-than-one-pipe-is-enabled.patch -- To unsubscribe from this list: send the line "unsubscribe mm-commits" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html