The patch titled
atmel_spi: fix clock polarity
has been added to the -mm tree. Its filename is
atmel_spi-fix-clock-polarity.patch
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------------------------------------------------------
Subject: atmel_spi: fix clock polarity
From: Atsushi Nemoto <anemo@xxxxxxxxxxxxx>
I found that atmel_spi driver does not initialize clock polarity correctly
(except for at91rm9200 CS0 channel) in some cases.
The atmel_spi driver uses gpio-controlled chipselect. OTOH spi clock
signal is controlled by CSRn.CPOL bit, but this register controls clock
signal correctly only in 'real transfer' duration. At the time of
cs_activate() call, CSRn.CPOL will be initialized correctly, but the
controller do not know which channel is to be used next, so clock signal
will stay at the inactive state of last transfer. If clock polarity of new
transfer and last transfer was differ, new transfer will start with wrong
clock signal state.
For example, if you started SPI MODE 2 or 3 transfer after SPI MODE 0 or 1
transfer, the clock signal state at the assertion of chipselect will be
low. Of course this will violates SPI transfer.
Here is my quick workaround for this problem. It makes all CSRn.CPOL match
for the transfer before activating chip select.
Cc: Haavard Skinnemoen <hskinnemoen@xxxxxxxxx>
Cc: David Brownell <david-b@xxxxxxxxxxx>
Signed-off-by: Andrew Morton <akpm@xxxxxxxxxxxxxxxxxxxx>
---
drivers/spi/atmel_spi.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff -puN drivers/spi/atmel_spi.c~atmel_spi-fix-clock-polarity drivers/spi/atmel_spi.c
--- a/drivers/spi/atmel_spi.c~atmel_spi-fix-clock-polarity
+++ a/drivers/spi/atmel_spi.c
@@ -87,6 +87,16 @@ static void cs_activate(struct atmel_spi
unsigned gpio = (unsigned) spi->controller_data;
unsigned active = spi->mode & SPI_CS_HIGH;
u32 mr;
+ int i;
+ u32 csr;
+ u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
+
+ /* Make sure clock polarity is correct */
+ for (i = 0; i < spi->master->num_chipselect; i++) {
+ csr = spi_readl(as, CSR0 + 4 * i);
+ if ((csr ^ cpol) & SPI_BIT(CPOL))
+ spi_writel(as, CSR0 + 4 * i, csr ^ SPI_BIT(CPOL));
+ }
mr = spi_readl(as, MR);
mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
_
Patches currently in -mm which might be from anemo@xxxxxxxxxxxxx are
git-watchdog.patch
atmel_spi-fix-clock-polarity.patch
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