The patch titled Subject: ia64: implement the new page table range API has been added to the -mm mm-unstable branch. Its filename is ia64-implement-the-new-page-table-range-api.patch This patch will shortly appear at https://git.kernel.org/pub/scm/linux/kernel/git/akpm/25-new.git/tree/patches/ia64-implement-the-new-page-table-range-api.patch This patch will later appear in the mm-unstable branch at git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm Before you just go and hit "reply", please: a) Consider who else should be cc'ed b) Prefer to cc a suitable mailing list as well c) Ideally: find the original patch on the mailing list and do a reply-to-all to that, adding suitable additional cc's *** Remember to use Documentation/process/submit-checklist.rst when testing your code *** The -mm tree is included into linux-next via the mm-everything branch at git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm and is updated there every 2-3 working days ------------------------------------------------------ From: "Matthew Wilcox (Oracle)" <willy@xxxxxxxxxxxxx> Subject: ia64: implement the new page table range API Date: Wed, 2 Aug 2023 16:13:41 +0100 Add PFN_PTE_SHIFT, update_mmu_cache_range() and flush_dcache_folio(). Change the PG_arch_1 (aka PG_dcache_clean) flag from being per-page to per-folio, which makes arch_dma_mark_clean() and mark_clean() a little more exciting. Link: https://lkml.kernel.org/r/20230802151406.3735276-14-willy@xxxxxxxxxxxxx Signed-off-by: Matthew Wilcox (Oracle) <willy@xxxxxxxxxxxxx> Acked-by: Mike Rapoport (IBM) <rppt@xxxxxxxxxx> Signed-off-by: Andrew Morton <akpm@xxxxxxxxxxxxxxxxxxxx> --- arch/ia64/hp/common/sba_iommu.c | 24 +++++++++++++---------- arch/ia64/include/asm/cacheflush.h | 14 +++++++++---- arch/ia64/include/asm/pgtable.h | 4 +-- arch/ia64/mm/init.c | 28 ++++++++++++++++++--------- 4 files changed, 45 insertions(+), 25 deletions(-) --- a/arch/ia64/hp/common/sba_iommu.c~ia64-implement-the-new-page-table-range-api +++ a/arch/ia64/hp/common/sba_iommu.c @@ -798,22 +798,26 @@ sba_io_pdir_entry(u64 *pdir_ptr, unsigne #endif #ifdef ENABLE_MARK_CLEAN -/** +/* * Since DMA is i-cache coherent, any (complete) pages that were written via * DMA can be marked as "clean" so that lazy_mmu_prot_update() doesn't have to * flush them when they get mapped into an executable vm-area. */ -static void -mark_clean (void *addr, size_t size) +static void mark_clean(void *addr, size_t size) { - unsigned long pg_addr, end; + struct folio *folio = virt_to_folio(addr); + ssize_t left = size; + size_t offset = offset_in_folio(folio, addr); - pg_addr = PAGE_ALIGN((unsigned long) addr); - end = (unsigned long) addr + size; - while (pg_addr + PAGE_SIZE <= end) { - struct page *page = virt_to_page((void *)pg_addr); - set_bit(PG_arch_1, &page->flags); - pg_addr += PAGE_SIZE; + if (offset) { + left -= folio_size(folio) - offset; + folio = folio_next(folio); + } + + while (left >= folio_size(folio)) { + set_bit(PG_arch_1, &folio->flags); + left -= folio_size(folio); + folio = folio_next(folio); } } #endif --- a/arch/ia64/include/asm/cacheflush.h~ia64-implement-the-new-page-table-range-api +++ a/arch/ia64/include/asm/cacheflush.h @@ -13,10 +13,16 @@ #include <asm/page.h> #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 -#define flush_dcache_page(page) \ -do { \ - clear_bit(PG_arch_1, &(page)->flags); \ -} while (0) +static inline void flush_dcache_folio(struct folio *folio) +{ + clear_bit(PG_arch_1, &folio->flags); +} +#define flush_dcache_folio flush_dcache_folio + +static inline void flush_dcache_page(struct page *page) +{ + flush_dcache_folio(page_folio(page)); +} extern void flush_icache_range(unsigned long start, unsigned long end); #define flush_icache_range flush_icache_range --- a/arch/ia64/include/asm/pgtable.h~ia64-implement-the-new-page-table-range-api +++ a/arch/ia64/include/asm/pgtable.h @@ -206,6 +206,7 @@ ia64_phys_addr_valid (unsigned long addr #define RGN_MAP_SHIFT (PGDIR_SHIFT + PTRS_PER_PGD_SHIFT - 3) #define RGN_MAP_LIMIT ((1UL << RGN_MAP_SHIFT) - PAGE_SIZE) /* per region addr limit */ +#define PFN_PTE_SHIFT PAGE_SHIFT /* * Conversion functions: convert page frame number (pfn) and a protection value to a page * table entry (pte). @@ -303,8 +304,6 @@ static inline void set_pte(pte_t *ptep, *ptep = pteval; } -#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) - /* * Make page protection values cacheable, uncacheable, or write- * combining. Note that "protection" is really a misnomer here as the @@ -396,6 +395,7 @@ pte_same (pte_t a, pte_t b) return pte_val(a) == pte_val(b); } +#define update_mmu_cache_range(vmf, vma, address, ptep, nr) do { } while (0) #define update_mmu_cache(vma, address, ptep) do { } while (0) extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; --- a/arch/ia64/mm/init.c~ia64-implement-the-new-page-table-range-api +++ a/arch/ia64/mm/init.c @@ -50,30 +50,40 @@ void __ia64_sync_icache_dcache (pte_t pte) { unsigned long addr; - struct page *page; + struct folio *folio; - page = pte_page(pte); - addr = (unsigned long) page_address(page); + folio = page_folio(pte_page(pte)); + addr = (unsigned long)folio_address(folio); - if (test_bit(PG_arch_1, &page->flags)) + if (test_bit(PG_arch_1, &folio->flags)) return; /* i-cache is already coherent with d-cache */ - flush_icache_range(addr, addr + page_size(page)); - set_bit(PG_arch_1, &page->flags); /* mark page as clean */ + flush_icache_range(addr, addr + folio_size(folio)); + set_bit(PG_arch_1, &folio->flags); /* mark page as clean */ } /* - * Since DMA is i-cache coherent, any (complete) pages that were written via + * Since DMA is i-cache coherent, any (complete) folios that were written via * DMA can be marked as "clean" so that lazy_mmu_prot_update() doesn't have to * flush them when they get mapped into an executable vm-area. */ void arch_dma_mark_clean(phys_addr_t paddr, size_t size) { unsigned long pfn = PHYS_PFN(paddr); + struct folio *folio = page_folio(pfn_to_page(pfn)); + ssize_t left = size; + size_t offset = offset_in_folio(folio, paddr); + + if (offset) { + left -= folio_size(folio) - offset; + folio = folio_next(folio); + } - do { + while (left >= (ssize_t)folio_size(folio)) { set_bit(PG_arch_1, &pfn_to_page(pfn)->flags); - } while (++pfn <= PHYS_PFN(paddr + size - 1)); + left -= folio_size(folio); + folio = folio_next(folio); + } } inline void _ Patches currently in -mm which might be from willy@xxxxxxxxxxxxx are mm-drop-per-vma-lock-when-returning-vm_fault_retry-or-vm_fault_completed-fix.patch rmap-pass-the-folio-to-__page_check_anon_rmap.patch highmem-add-memcpy_to_folio-and-memcpy_from_folio.patch affs-convert-affs_symlink_read_folio-to-use-the-folio.patch affs-convert-data-read-and-write-to-use-folios.patch migrate-use-folio_set_bh-instead-of-set_bh_page.patch ntfs3-convert-ntfs_get_block_vbo-to-use-a-folio.patch jbd2-use-a-folio-in-jbd2_journal_write_metadata_buffer.patch buffer-remove-set_bh_page.patch zswap-make-zswap_store-take-a-folio.patch memcg-convert-get_obj_cgroup_from_page-to-get_obj_cgroup_from_folio.patch swap-remove-some-calls-to-compound_head-in-swap_readpage.patch zswap-make-zswap_load-take-a-folio.patch mm-remove-config_per_vma_lock-ifdefs.patch mm-allow-per-vma-locks-on-file-backed-vmas.patch mm-move-fault_flag_vma_lock-check-from-handle_mm_fault.patch mm-handle-pud-faults-under-the-vma-lock.patch mm-handle-some-pmd-faults-under-the-vma-lock.patch mm-move-fault_flag_vma_lock-check-down-in-handle_pte_fault.patch mm-move-fault_flag_vma_lock-check-down-from-do_fault.patch mm-run-the-fault-around-code-under-the-vma-lock.patch mm-handle-swap-and-numa-pte-faults-under-the-vma-lock.patch mm-handle-faults-that-merely-update-the-accessed-bit-under-the-vma-lock.patch mm-handle-faults-that-merely-update-the-accessed-bit-under-the-vma-lock-fix.patch mm-improve-the-comment-in-isolate_migratepages_block.patch minmax-add-in_range-macro.patch mm-convert-page_table_check_pte_set-to-page_table_check_ptes_set.patch mm-add-generic-flush_icache_pages-and-documentation.patch mm-add-folio_flush_mapping.patch mm-remove-arch_implements_flush_dcache_folio.patch mm-add-default-definition-of-set_ptes.patch alpha-implement-the-new-page-table-range-api.patch arc-implement-the-new-page-table-range-api.patch arm-implement-the-new-page-table-range-api.patch arm64-implement-the-new-page-table-range-api.patch csky-implement-the-new-page-table-range-api.patch hexagon-implement-the-new-page-table-range-api.patch ia64-implement-the-new-page-table-range-api.patch loongarch-implement-the-new-page-table-range-api.patch m68k-implement-the-new-page-table-range-api.patch microblaze-implement-the-new-page-table-range-api.patch mips-implement-the-new-page-table-range-api.patch nios2-implement-the-new-page-table-range-api.patch openrisc-implement-the-new-page-table-range-api.patch parisc-implement-the-new-page-table-range-api.patch powerpc-implement-the-new-page-table-range-api.patch riscv-implement-the-new-page-table-range-api.patch s390-implement-the-new-page-table-range-api.patch sh-implement-the-new-page-table-range-api.patch sparc32-implement-the-new-page-table-range-api.patch sparc64-implement-the-new-page-table-range-api.patch um-implement-the-new-page-table-range-api.patch x86-implement-the-new-page-table-range-api.patch xtensa-implement-the-new-page-table-range-api.patch mm-remove-page_mapping_file.patch mm-rationalise-flush_icache_pages-and-flush_icache_page.patch mm-tidy-up-set_ptes-definition.patch mm-use-flush_icache_pages-in-do_set_pmd.patch mm-call-update_mmu_cache_range-in-more-page-fault-handling-paths.patch