The patch titled
i386 add X86_FEATURE_PEBS and detection
has been added to the -mm tree. Its filename is
i386-add-x86_feature_pebs-and-detection.patch
See http://www.zip.com.au/~akpm/linux/patches/stuff/added-to-mm.txt to find
out what to do about this
------------------------------------------------------
Subject: i386 add X86_FEATURE_PEBS and detection
From: Stephane Eranian <eranian@xxxxxxxxxx>
Here is a patch (used by perfmon2) to detect the presence of the Precise Event
Based Sampling (PEBS) feature for i386. The patch also adds the cpu_has_pebs
macro.
- adds X86_FEATURE_PEBS
- adds cpu_has_pebs to test for X86_FEATURE_PEBS
Signed-off-by: stephane eranian <eranian@xxxxxxxxxx>
Cc: Andi Kleen <ak@xxxxxxx>
Signed-off-by: Andrew Morton <akpm@xxxxxxxx>
---
arch/i386/kernel/cpu/intel.c | 8 +++++++-
include/asm-i386/cpufeature.h | 2 ++
2 files changed, 9 insertions(+), 1 deletion(-)
diff -puN arch/i386/kernel/cpu/intel.c~i386-add-x86_feature_pebs-and-detection arch/i386/kernel/cpu/intel.c
--- a/arch/i386/kernel/cpu/intel.c~i386-add-x86_feature_pebs-and-detection
+++ a/arch/i386/kernel/cpu/intel.c
@@ -195,8 +195,14 @@ static void __cpuinit init_intel(struct
if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
(c->x86 == 0x6 && c->x86_model >= 0x0e))
set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
-}
+ if (cpu_has_ds) {
+ unsigned int l1;
+ rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
+ if (!(l1 & (1<<12)))
+ set_bit(X86_FEATURE_PEBS, c->x86_capability);
+ }
+}
static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 * c, unsigned int size)
{
diff -puN include/asm-i386/cpufeature.h~i386-add-x86_feature_pebs-and-detection include/asm-i386/cpufeature.h
--- a/include/asm-i386/cpufeature.h~i386-add-x86_feature_pebs-and-detection
+++ a/include/asm-i386/cpufeature.h
@@ -73,6 +73,7 @@
#define X86_FEATURE_UP (3*32+ 9) /* smp kernel running on up */
#define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* FXSAVE leaks FOP/FIP/FOP */
#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
+#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */
/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
@@ -135,6 +136,7 @@
#define cpu_has_pmm boot_cpu_has(X86_FEATURE_PMM)
#define cpu_has_pmm_enabled boot_cpu_has(X86_FEATURE_PMM_EN)
#define cpu_has_ds boot_cpu_has(X86_FEATURE_DS)
+#define cpu_has_pebs boot_cpu_has(X86_FEATURE_PEBS)
#endif /* __ASM_I386_CPUFEATURE_H */
_
Patches currently in -mm which might be from eranian@xxxxxxxxxx are
x86_64-add-missing-enter_idle-calls.patch
x86_64-rename-x86_feature_dtes-to-x86_feature_ds.patch
add-x86_feature_pebs-and-detection.patch
i386-rename-x86_feature_dtes-to-x86_feature_ds.patch
i386-add-x86_feature_pebs-and-detection.patch
adds-carta_random32-library-routine.patch
-
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