+ add-x86_feature_pebs-and-detection.patch added to -mm tree

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The patch titled

     add X86_FEATURE_PEBS and detection

has been added to the -mm tree.  Its filename is

     add-x86_feature_pebs-and-detection.patch

See http://www.zip.com.au/~akpm/linux/patches/stuff/added-to-mm.txt to find
out what to do about this

------------------------------------------------------
Subject: add X86_FEATURE_PEBS and detection
From: Stephane Eranian <eranian@xxxxxxxxxx>

Here is a patch (used by perfmon2) to detect the presence of the Precise Event
Based Sampling (PEBS) feature for Intel 64-bit processors.  The patch also
adds the cpu_has_pebs macro.

- adds X86_FEATURE_PEBS

- adds cpu_has_pebs to test for X86_FEATURE_PEBS

Signed-off-by: stephane eranian <eranian@xxxxxxxxxx>
Cc: Andi Kleen <ak@xxxxxxx>
Signed-off-by: Andrew Morton <akpm@xxxxxxxx>
---

 arch/x86_64/kernel/setup.c      |    7 +++++++
 include/asm-x86_64/cpufeature.h |    2 ++
 2 files changed, 9 insertions(+)

diff -puN arch/x86_64/kernel/setup.c~add-x86_feature_pebs-and-detection arch/x86_64/kernel/setup.c
--- a/arch/x86_64/kernel/setup.c~add-x86_feature_pebs-and-detection
+++ a/arch/x86_64/kernel/setup.c
@@ -835,6 +835,13 @@ static void __cpuinit init_intel(struct 
 			set_bit(X86_FEATURE_ARCH_PERFMON, &c->x86_capability);
 	}
 
+	if (cpu_has_ds) {
+		unsigned int l1, l2;
+		rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
+		if (!(l1 & (1<<12)))
+			set_bit(X86_FEATURE_PEBS, c->x86_capability);
+	}
+
 	n = c->extended_cpuid_level;
 	if (n >= 0x80000008) {
 		unsigned eax = cpuid_eax(0x80000008);
diff -puN include/asm-x86_64/cpufeature.h~add-x86_feature_pebs-and-detection include/asm-x86_64/cpufeature.h
--- a/include/asm-x86_64/cpufeature.h~add-x86_feature_pebs-and-detection
+++ a/include/asm-x86_64/cpufeature.h
@@ -68,6 +68,7 @@
 #define X86_FEATURE_FXSAVE_LEAK (3*32+7)  /* FIP/FOP/FDP leaks through FXSAVE */
 #define X86_FEATURE_UP		(3*32+8) /* SMP kernel running on UP */
 #define X86_FEATURE_ARCH_PERFMON (3*32+9) /* Intel Architectural PerfMon */
+#define X86_FEATURE_PEBS	(3*32+10) /* Precise-Event Based Sampling */
 
 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
 #define X86_FEATURE_XMM3	(4*32+ 0) /* Streaming SIMD Extensions-3 */
@@ -113,5 +114,6 @@
 #define cpu_has_centaur_mcr    0
 #define cpu_has_clflush	       boot_cpu_has(X86_FEATURE_CLFLSH)
 #define cpu_has_ds 	       boot_cpu_has(X86_FEATURE_DS)
+#define cpu_has_pebs 	       boot_cpu_has(X86_FEATURE_PEBS)
 
 #endif /* __ASM_X8664_CPUFEATURE_H */
_

Patches currently in -mm which might be from eranian@xxxxxxxxxx are

x86_64-add-missing-enter_idle-calls.patch
x86_64-rename-x86_feature_dtes-to-x86_feature_ds.patch
add-x86_feature_pebs-and-detection.patch
i386-rename-x86_feature_dtes-to-x86_feature_ds.patch
i386-add-x86_feature_pebs-and-detection.patch
adds-carta_random32-library-routine.patch

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