[merged] sh-prefix-sh-specific-ccr-and-ccr2-by-sh_.patch removed from -mm tree

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Subject: [merged] sh-prefix-sh-specific-ccr-and-ccr2-by-sh_.patch removed from -mm tree
To: geert@xxxxxxxxxxxxxx,mm-commits@xxxxxxxxxxxxxxx
From: akpm@xxxxxxxxxxxxxxxxxxxx
Date: Thu, 06 Mar 2014 12:37:44 -0800


The patch titled
     Subject: sh: prefix sh-specific "CCR" and "CCR2" by "SH_"
has been removed from the -mm tree.  Its filename was
     sh-prefix-sh-specific-ccr-and-ccr2-by-sh_.patch

This patch was dropped because it was merged into mainline or a subsystem tree

------------------------------------------------------
From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>
Subject: sh: prefix sh-specific "CCR" and "CCR2" by "SH_"

bcf24e1daa94f ("mmc: omap_hsmmc: use the generic config for omap2plus
devices"), enabled the build for other platforms for compile testing.

sh-allmodconfig now fails with:

    include/linux/omap-dma.h:171:8: error: expected identifier before numeric constant
    make[4]: *** [drivers/mmc/host/omap_hsmmc.o] Error 1

This happens because SuperH #defines "CCR", which is one of the enum
values in include/linux/omap-dma.h.  There's a similar issue with "CCR2"
on sh2a.

As "CCR" and "CCR2" are too generic names for global #defines, prefix them
with "SH_" to fix this.

Signed-off-by: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>
Signed-off-by: Andrew Morton <akpm@xxxxxxxxxxxxxxxxxxxx>
---

 arch/sh/include/cpu-sh2/cpu/cache.h  |    2 +-
 arch/sh/include/cpu-sh2a/cpu/cache.h |    4 ++--
 arch/sh/include/cpu-sh3/cpu/cache.h  |    2 +-
 arch/sh/include/cpu-sh4/cpu/cache.h  |    2 +-
 arch/sh/kernel/cpu/init.c            |    4 ++--
 arch/sh/mm/cache-debugfs.c           |    2 +-
 arch/sh/mm/cache-sh2.c               |    4 ++--
 arch/sh/mm/cache-sh2a.c              |    6 ++++--
 arch/sh/mm/cache-sh4.c               |    4 ++--
 arch/sh/mm/cache-shx3.c              |    4 ++--
 arch/sh/mm/cache.c                   |    4 ++--
 11 files changed, 20 insertions(+), 18 deletions(-)

diff -puN arch/sh/include/cpu-sh2/cpu/cache.h~sh-prefix-sh-specific-ccr-and-ccr2-by-sh_ arch/sh/include/cpu-sh2/cpu/cache.h
--- a/arch/sh/include/cpu-sh2/cpu/cache.h~sh-prefix-sh-specific-ccr-and-ccr2-by-sh_
+++ a/arch/sh/include/cpu-sh2/cpu/cache.h
@@ -18,7 +18,7 @@
 #define SH_CACHE_ASSOC		8
 
 #if defined(CONFIG_CPU_SUBTYPE_SH7619)
-#define CCR		0xffffffec
+#define SH_CCR		0xffffffec
 
 #define CCR_CACHE_CE	0x01	/* Cache enable */
 #define CCR_CACHE_WT	0x02    /* CCR[bit1=1,bit2=1] */
diff -puN arch/sh/include/cpu-sh2a/cpu/cache.h~sh-prefix-sh-specific-ccr-and-ccr2-by-sh_ arch/sh/include/cpu-sh2a/cpu/cache.h
--- a/arch/sh/include/cpu-sh2a/cpu/cache.h~sh-prefix-sh-specific-ccr-and-ccr2-by-sh_
+++ a/arch/sh/include/cpu-sh2a/cpu/cache.h
@@ -17,8 +17,8 @@
 #define SH_CACHE_COMBINED	4
 #define SH_CACHE_ASSOC		8
 
-#define CCR		0xfffc1000 /* CCR1 */
-#define CCR2		0xfffc1004
+#define SH_CCR		0xfffc1000 /* CCR1 */
+#define SH_CCR2		0xfffc1004
 
 /*
  * Most of the SH-2A CCR1 definitions resemble the SH-4 ones. All others not
diff -puN arch/sh/include/cpu-sh3/cpu/cache.h~sh-prefix-sh-specific-ccr-and-ccr2-by-sh_ arch/sh/include/cpu-sh3/cpu/cache.h
--- a/arch/sh/include/cpu-sh3/cpu/cache.h~sh-prefix-sh-specific-ccr-and-ccr2-by-sh_
+++ a/arch/sh/include/cpu-sh3/cpu/cache.h
@@ -17,7 +17,7 @@
 #define SH_CACHE_COMBINED	4
 #define SH_CACHE_ASSOC		8
 
-#define CCR		0xffffffec	/* Address of Cache Control Register */
+#define SH_CCR		0xffffffec	/* Address of Cache Control Register */
 
 #define CCR_CACHE_CE	0x01	/* Cache Enable */
 #define CCR_CACHE_WT	0x02	/* Write-Through (for P0,U0,P3) (else writeback) */
diff -puN arch/sh/include/cpu-sh4/cpu/cache.h~sh-prefix-sh-specific-ccr-and-ccr2-by-sh_ arch/sh/include/cpu-sh4/cpu/cache.h
--- a/arch/sh/include/cpu-sh4/cpu/cache.h~sh-prefix-sh-specific-ccr-and-ccr2-by-sh_
+++ a/arch/sh/include/cpu-sh4/cpu/cache.h
@@ -17,7 +17,7 @@
 #define SH_CACHE_COMBINED	4
 #define SH_CACHE_ASSOC		8
 
-#define CCR		0xff00001c	/* Address of Cache Control Register */
+#define SH_CCR		0xff00001c	/* Address of Cache Control Register */
 #define CCR_CACHE_OCE	0x0001	/* Operand Cache Enable */
 #define CCR_CACHE_WT	0x0002	/* Write-Through (for P0,U0,P3) (else writeback)*/
 #define CCR_CACHE_CB	0x0004	/* Copy-Back (for P1) (else writethrough) */
diff -puN arch/sh/kernel/cpu/init.c~sh-prefix-sh-specific-ccr-and-ccr2-by-sh_ arch/sh/kernel/cpu/init.c
--- a/arch/sh/kernel/cpu/init.c~sh-prefix-sh-specific-ccr-and-ccr2-by-sh_
+++ a/arch/sh/kernel/cpu/init.c
@@ -112,7 +112,7 @@ static void cache_init(void)
 	unsigned long ccr, flags;
 
 	jump_to_uncached();
-	ccr = __raw_readl(CCR);
+	ccr = __raw_readl(SH_CCR);
 
 	/*
 	 * At this point we don't know whether the cache is enabled or not - a
@@ -189,7 +189,7 @@ static void cache_init(void)
 
 	l2_cache_init();
 
-	__raw_writel(flags, CCR);
+	__raw_writel(flags, SH_CCR);
 	back_to_cached();
 }
 #else
diff -puN arch/sh/mm/cache-debugfs.c~sh-prefix-sh-specific-ccr-and-ccr2-by-sh_ arch/sh/mm/cache-debugfs.c
--- a/arch/sh/mm/cache-debugfs.c~sh-prefix-sh-specific-ccr-and-ccr2-by-sh_
+++ a/arch/sh/mm/cache-debugfs.c
@@ -36,7 +36,7 @@ static int cache_seq_show(struct seq_fil
 	 */
 	jump_to_uncached();
 
-	ccr = __raw_readl(CCR);
+	ccr = __raw_readl(SH_CCR);
 	if ((ccr & CCR_CACHE_ENABLE) == 0) {
 		back_to_cached();
 
diff -puN arch/sh/mm/cache-sh2.c~sh-prefix-sh-specific-ccr-and-ccr2-by-sh_ arch/sh/mm/cache-sh2.c
--- a/arch/sh/mm/cache-sh2.c~sh-prefix-sh-specific-ccr-and-ccr2-by-sh_
+++ a/arch/sh/mm/cache-sh2.c
@@ -63,9 +63,9 @@ static void sh2__flush_invalidate_region
 	local_irq_save(flags);
 	jump_to_uncached();
 
-	ccr = __raw_readl(CCR);
+	ccr = __raw_readl(SH_CCR);
 	ccr |= CCR_CACHE_INVALIDATE;
-	__raw_writel(ccr, CCR);
+	__raw_writel(ccr, SH_CCR);
 
 	back_to_cached();
 	local_irq_restore(flags);
diff -puN arch/sh/mm/cache-sh2a.c~sh-prefix-sh-specific-ccr-and-ccr2-by-sh_ arch/sh/mm/cache-sh2a.c
--- a/arch/sh/mm/cache-sh2a.c~sh-prefix-sh-specific-ccr-and-ccr2-by-sh_
+++ a/arch/sh/mm/cache-sh2a.c
@@ -134,7 +134,8 @@ static void sh2a__flush_invalidate_regio
 
 	/* If there are too many pages then just blow the cache */
 	if (((end - begin) >> PAGE_SHIFT) >= MAX_OCACHE_PAGES) {
-		__raw_writel(__raw_readl(CCR) | CCR_OCACHE_INVALIDATE, CCR);
+		__raw_writel(__raw_readl(SH_CCR) | CCR_OCACHE_INVALIDATE,
+			     SH_CCR);
 	} else {
 		for (v = begin; v < end; v += L1_CACHE_BYTES)
 			sh2a_invalidate_line(CACHE_OC_ADDRESS_ARRAY, v);
@@ -167,7 +168,8 @@ static void sh2a_flush_icache_range(void
 	/* I-Cache invalidate */
 	/* If there are too many pages then just blow the cache */
 	if (((end - start) >> PAGE_SHIFT) >= MAX_ICACHE_PAGES) {
-		__raw_writel(__raw_readl(CCR) | CCR_ICACHE_INVALIDATE, CCR);
+		__raw_writel(__raw_readl(SH_CCR) | CCR_ICACHE_INVALIDATE,
+			     SH_CCR);
 	} else {
 		for (v = start; v < end; v += L1_CACHE_BYTES)
 			sh2a_invalidate_line(CACHE_IC_ADDRESS_ARRAY, v);
diff -puN arch/sh/mm/cache-sh4.c~sh-prefix-sh-specific-ccr-and-ccr2-by-sh_ arch/sh/mm/cache-sh4.c
--- a/arch/sh/mm/cache-sh4.c~sh-prefix-sh-specific-ccr-and-ccr2-by-sh_
+++ a/arch/sh/mm/cache-sh4.c
@@ -133,9 +133,9 @@ static void flush_icache_all(void)
 	jump_to_uncached();
 
 	/* Flush I-cache */
-	ccr = __raw_readl(CCR);
+	ccr = __raw_readl(SH_CCR);
 	ccr |= CCR_CACHE_ICI;
-	__raw_writel(ccr, CCR);
+	__raw_writel(ccr, SH_CCR);
 
 	/*
 	 * back_to_cached() will take care of the barrier for us, don't add
diff -puN arch/sh/mm/cache-shx3.c~sh-prefix-sh-specific-ccr-and-ccr2-by-sh_ arch/sh/mm/cache-shx3.c
--- a/arch/sh/mm/cache-shx3.c~sh-prefix-sh-specific-ccr-and-ccr2-by-sh_
+++ a/arch/sh/mm/cache-shx3.c
@@ -19,7 +19,7 @@ void __init shx3_cache_init(void)
 {
 	unsigned int ccr;
 
-	ccr = __raw_readl(CCR);
+	ccr = __raw_readl(SH_CCR);
 
 	/*
 	 * If we've got cache aliases, resolve them in hardware.
@@ -40,5 +40,5 @@ void __init shx3_cache_init(void)
 	ccr |= CCR_CACHE_IBE;
 #endif
 
-	writel_uncached(ccr, CCR);
+	writel_uncached(ccr, SH_CCR);
 }
diff -puN arch/sh/mm/cache.c~sh-prefix-sh-specific-ccr-and-ccr2-by-sh_ arch/sh/mm/cache.c
--- a/arch/sh/mm/cache.c~sh-prefix-sh-specific-ccr-and-ccr2-by-sh_
+++ a/arch/sh/mm/cache.c
@@ -285,8 +285,8 @@ void __init cpu_cache_init(void)
 {
 	unsigned int cache_disabled = 0;
 
-#ifdef CCR
-	cache_disabled = !(__raw_readl(CCR) & CCR_CACHE_ENABLE);
+#ifdef SH_CCR
+	cache_disabled = !(__raw_readl(SH_CCR) & CCR_CACHE_ENABLE);
 #endif
 
 	compute_alias(&boot_cpu_data.icache);
_

Patches currently in -mm which might be from geert@xxxxxxxxxxxxxx are

origin.patch
arch-sh-boards-board-sh7757lcrc-fixup-sdhi-register-size.patch
cris-cpuinfo_op-should-depend-on-config_proc_fs.patch
linux-next.patch

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