The patch titled
EHCI works again on NVidia controllers with >2GB RAM
has been removed from the -mm tree. Its filename is
ehci-works-again-on-nvidia-controllers-with-2gb-ram.patch
This patch was dropped because it was merged into mainline or a subsystem tree
------------------------------------------------------
Subject: EHCI works again on NVidia controllers with >2GB RAM
From: Paul Serice <paul@xxxxxxxxxx>
The workaround in commit f7201c3dcd7799f2aa3d6ec427b194225360ecee broke.
The work around requires memory for DMA transfers for some NVidia EHCI
controllers to be below 2GB, but recent changes have caused some DMA memory
to be allocated before the DMA mask is set.
Signed-off-by: Paul Serice <paul@xxxxxxxxxx>
Signed-off-by: David Brownell <dbrownell@xxxxxxxxxxxxxxxxxxxxx>
Cc: Greg KH <greg@xxxxxxxxx>
Signed-off-by: Andrew Morton <akpm@xxxxxxxx>
---
drivers/usb/host/ehci-pci.c | 39 ++++++++++++++++++++--------------
1 file changed, 24 insertions(+), 15 deletions(-)
diff -puN drivers/usb/host/ehci-pci.c~ehci-works-again-on-nvidia-controllers-with-2gb-ram drivers/usb/host/ehci-pci.c
--- devel/drivers/usb/host/ehci-pci.c~ehci-works-again-on-nvidia-controllers-with-2gb-ram 2006-06-07 23:52:03.000000000 -0700
+++ devel-akpm/drivers/usb/host/ehci-pci.c 2006-06-07 23:52:03.000000000 -0700
@@ -76,6 +76,30 @@ static int ehci_pci_setup(struct usb_hcd
dbg_hcs_params(ehci, "reset");
dbg_hcc_params(ehci, "reset");
+ /* ehci_init() causes memory for DMA transfers to be
+ * allocated. Thus, any vendor-specific workarounds based on
+ * limiting the type of memory used for DMA transfers must
+ * happen before ehci_init() is called. */
+ switch (pdev->vendor) {
+ case PCI_VENDOR_ID_NVIDIA:
+ /* NVidia reports that certain chips don't handle
+ * QH, ITD, or SITD addresses above 2GB. (But TD,
+ * data buffer, and periodic schedule are normal.)
+ */
+ switch (pdev->device) {
+ case 0x003c: /* MCP04 */
+ case 0x005b: /* CK804 */
+ case 0x00d8: /* CK8 */
+ case 0x00e8: /* CK8S */
+ if (pci_set_consistent_dma_mask(pdev,
+ DMA_31BIT_MASK) < 0)
+ ehci_warn(ehci, "can't enable NVidia "
+ "workaround for >2GB RAM\n");
+ break;
+ }
+ break;
+ }
+
/* cache this readonly data; minimize chip reads */
ehci->hcs_params = readl(&ehci->caps->hcs_params);
@@ -88,8 +112,6 @@ static int ehci_pci_setup(struct usb_hcd
if (retval)
return retval;
- /* NOTE: only the parts below this line are PCI-specific */
-
switch (pdev->vendor) {
case PCI_VENDOR_ID_TDI:
if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
@@ -107,19 +129,6 @@ static int ehci_pci_setup(struct usb_hcd
break;
case PCI_VENDOR_ID_NVIDIA:
switch (pdev->device) {
- /* NVidia reports that certain chips don't handle
- * QH, ITD, or SITD addresses above 2GB. (But TD,
- * data buffer, and periodic schedule are normal.)
- */
- case 0x003c: /* MCP04 */
- case 0x005b: /* CK804 */
- case 0x00d8: /* CK8 */
- case 0x00e8: /* CK8S */
- if (pci_set_consistent_dma_mask(pdev,
- DMA_31BIT_MASK) < 0)
- ehci_warn(ehci, "can't enable NVidia "
- "workaround for >2GB RAM\n");
- break;
/* Some NForce2 chips have problems with selective suspend;
* fixed in newer silicon.
*/
_
Patches currently in -mm which might be from paul@xxxxxxxxxx are
origin.patch
-
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