The patch titled
x86_64: avoid IRQ0 ioapic pin collision
has been removed from the -mm tree. Its filename is
x86_64-avoid-irq0-ioapic-pin-collision.patch
This patch was probably dropped from -mm because
it has now been merged into a subsystem tree or
into Linus's tree, or because it was folded into
its parent patch in the -mm tree.
From: Kimball Murray <kimball.murray@xxxxxxxxx>
The patch addresses a problem with ACPI SCI interrupt entry, which gets
re-used, and the IRQ is assigned to another unrelated device. The patch
corrects the code such that SCI IRQ is skipped and duplicate entry is avoided.
Second issue came up with VIA chipset, the problem was caused by original
patch assigning IRQs starting 16 and up. The VIA chipset uses 4-bit IRQ
register for internal interrupt routing, and therefore cannot handle IRQ
numbers assigned to its devices. The patch corrects this problem by allowing
PCI IRQs below 16.
Cc: Len Broen <len.brown@xxxxxxxxx>
Signed-off by: Natalie Protasevich <Natalie.Protasevich@xxxxxxxxxx>
Signed-off-by: Andi Kleen <ak@xxxxxxx>
Signed-off-by: Andrew Morton <akpm@xxxxxxxx>
---
arch/i386/kernel/io_apic.c | 5 +++++
arch/i386/kernel/mpparse.c | 12 +++++++++++-
arch/x86_64/kernel/io_apic.c | 5 +++++
arch/x86_64/kernel/mpparse.c | 12 +++++++++++-
include/asm-i386/io_apic.h | 1 +
include/asm-x86_64/io_apic.h | 1 +
6 files changed, 34 insertions(+), 2 deletions(-)
diff -puN arch/i386/kernel/io_apic.c~x86_64-avoid-irq0-ioapic-pin-collision arch/i386/kernel/io_apic.c
--- devel/arch/i386/kernel/io_apic.c~x86_64-avoid-irq0-ioapic-pin-collision 2006-05-10 21:18:04.000000000 -0700
+++ devel-akpm/arch/i386/kernel/io_apic.c 2006-05-10 21:18:04.000000000 -0700
@@ -2238,6 +2238,8 @@ static inline void unlock_ExtINT_logic(v
spin_unlock_irqrestore(&ioapic_lock, flags);
}
+int timer_uses_ioapic_pin_0;
+
/*
* This code may look a bit paranoid, but it's supposed to cooperate with
* a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
@@ -2274,6 +2276,9 @@ static inline void check_timer(void)
pin2 = ioapic_i8259.pin;
apic2 = ioapic_i8259.apic;
+ if (pin1 == 0)
+ timer_uses_ioapic_pin_0 = 1;
+
printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
vector, apic1, pin1, apic2, pin2);
diff -puN arch/i386/kernel/mpparse.c~x86_64-avoid-irq0-ioapic-pin-collision arch/i386/kernel/mpparse.c
--- devel/arch/i386/kernel/mpparse.c~x86_64-avoid-irq0-ioapic-pin-collision 2006-05-10 21:18:04.000000000 -0700
+++ devel-akpm/arch/i386/kernel/mpparse.c 2006-05-10 21:18:04.000000000 -0700
@@ -1130,7 +1130,17 @@ int mp_register_gsi (u32 gsi, int trigge
*/
int irq = gsi;
if (gsi < MAX_GSI_NUM) {
- if (gsi > 15)
+ /*
+ * Retain the VIA chipset work-around (gsi > 15), but
+ * avoid a problem where the 8254 timer (IRQ0) is setup
+ * via an override (so it's not on pin 0 of the ioapic),
+ * and at the same time, the pin 0 interrupt is a PCI
+ * type. The gsi > 15 test could cause these two pins
+ * to be shared as IRQ0, and they are not shareable.
+ * So test for this condition, and if necessary, avoid
+ * the pin collision.
+ */
+ if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0))
gsi = pci_irq++;
/*
* Don't assign IRQ used by ACPI SCI
diff -puN arch/x86_64/kernel/io_apic.c~x86_64-avoid-irq0-ioapic-pin-collision arch/x86_64/kernel/io_apic.c
--- devel/arch/x86_64/kernel/io_apic.c~x86_64-avoid-irq0-ioapic-pin-collision 2006-05-10 21:18:04.000000000 -0700
+++ devel-akpm/arch/x86_64/kernel/io_apic.c 2006-05-10 21:18:04.000000000 -0700
@@ -1777,6 +1777,8 @@ static inline void unlock_ExtINT_logic(v
spin_unlock_irqrestore(&ioapic_lock, flags);
}
+int timer_uses_ioapic_pin_0;
+
/*
* This code may look a bit paranoid, but it's supposed to cooperate with
* a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
@@ -1814,6 +1816,9 @@ static inline void check_timer(void)
pin2 = ioapic_i8259.pin;
apic2 = ioapic_i8259.apic;
+ if (pin1 == 0)
+ timer_uses_ioapic_pin_0 = 1;
+
apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
vector, apic1, pin1, apic2, pin2);
diff -puN arch/x86_64/kernel/mpparse.c~x86_64-avoid-irq0-ioapic-pin-collision arch/x86_64/kernel/mpparse.c
--- devel/arch/x86_64/kernel/mpparse.c~x86_64-avoid-irq0-ioapic-pin-collision 2006-05-10 21:18:04.000000000 -0700
+++ devel-akpm/arch/x86_64/kernel/mpparse.c 2006-05-10 21:18:04.000000000 -0700
@@ -968,7 +968,17 @@ int mp_register_gsi(u32 gsi, int trigger
*/
int irq = gsi;
if (gsi < MAX_GSI_NUM) {
- if (gsi > 15)
+ /*
+ * Retain the VIA chipset work-around (gsi > 15), but
+ * avoid a problem where the 8254 timer (IRQ0) is setup
+ * via an override (so it's not on pin 0 of the ioapic),
+ * and at the same time, the pin 0 interrupt is a PCI
+ * type. The gsi > 15 test could cause these two pins
+ * to be shared as IRQ0, and they are not shareable.
+ * So test for this condition, and if necessary, avoid
+ * the pin collision.
+ */
+ if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0))
gsi = pci_irq++;
/*
* Don't assign IRQ used by ACPI SCI
diff -puN include/asm-i386/io_apic.h~x86_64-avoid-irq0-ioapic-pin-collision include/asm-i386/io_apic.h
--- devel/include/asm-i386/io_apic.h~x86_64-avoid-irq0-ioapic-pin-collision 2006-05-10 21:18:04.000000000 -0700
+++ devel-akpm/include/asm-i386/io_apic.h 2006-05-10 21:18:04.000000000 -0700
@@ -200,6 +200,7 @@ extern int io_apic_get_unique_id (int io
extern int io_apic_get_version (int ioapic);
extern int io_apic_get_redir_entries (int ioapic);
extern int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low);
+extern int timer_uses_ioapic_pin_0;
#endif /* CONFIG_ACPI */
extern int (*ioapic_renumber_irq)(int ioapic, int irq);
diff -puN include/asm-x86_64/io_apic.h~x86_64-avoid-irq0-ioapic-pin-collision include/asm-x86_64/io_apic.h
--- devel/include/asm-x86_64/io_apic.h~x86_64-avoid-irq0-ioapic-pin-collision 2006-05-10 21:18:04.000000000 -0700
+++ devel-akpm/include/asm-x86_64/io_apic.h 2006-05-10 21:18:04.000000000 -0700
@@ -205,6 +205,7 @@ extern int skip_ioapic_setup;
extern int io_apic_get_version (int ioapic);
extern int io_apic_get_redir_entries (int ioapic);
extern int io_apic_set_pci_routing (int ioapic, int pin, int irq, int, int);
+extern int timer_uses_ioapic_pin_0;
#endif
extern int sis_apic_bug; /* dummy */
_
Patches currently in -mm which might be from kimball.murray@xxxxxxxxx are
origin.patch
-
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