On Fri, Jul 31, 2020 at 03:49:28PM -0700, Florian Fainelli wrote:
> On 7/31/20 3:34 AM, Jiaxun Yang wrote:
> >
> >
> > 在 2020/7/31 下午12:24, Florian Fainelli 写道:
> >> Disable pref 30 by utilizing the standard quirk method and matching the
> >> affected SoCs: 7344, 7346, 7425.
> >>
> >> Signed-off-by: Florian Fainelli <f.fainelli@xxxxxxxxx>
> >> ---
> >> arch/mips/bmips/setup.c | 17 +++++++++++++++++
> >> 1 file changed, 17 insertions(+)
> >>
> >> diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c
> >> index 19308df5f577..df0efea12611 100644
> >> --- a/arch/mips/bmips/setup.c
> >> +++ b/arch/mips/bmips/setup.c
> >> @@ -110,6 +110,20 @@ static void bcm6368_quirks(void)
> >> bcm63xx_fixup_cpu1();
> >> }
> >> +static void bmips5000_pref30_quirk(void)
> >> +{
> >> + __asm__ __volatile__(
> >> + " li $8, 0x5a455048\n"
> >> + " .word 0x4088b00f\n" /* mtc0 $8, $22, 15 */
> >> + " nop; nop; nop\n"
> >> + " .word 0x4008b008\n" /* mfc0 $8, $22, 8 */
> >> + /* disable "pref 30" on buggy CPUs */
> >> + " lui $9, 0x0800\n"
> >> + " or $8, $9\n"
> >> + " .word 0x4088b008\n" /* mtc0 $8, $22, 8 */
> >> + : : : "$8", "$9");
> >> +}
> > Hi,
> >
> > Is there any toolchain issue blocking read_c0_**** family helpers being
> > used?
> >
> > Use .word looks unreasonable.
>
> Yes, the assembler would be choking on the custom $22 selector, however
I guess you meant selector 8 and 15. If BMIPS has a 4 bit selector field
it might be good to do a binutils patch supporting it.
> this patch should not be necessary given that the boot loader (CFE)
> should have long been updated by now to disable pref 30.
so, should I add it or drop it ?
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
