From: Marcin Nowakowski <marcin.nowakowski@xxxxxxxxxx>
commit f7a31b5e7874f77464a4eae0a8ba84b9ae0b3a54 upstream.
All performance counters on I6400 (odd and even) are capable of counting
any of the available events, so drop current logic of using the extra
bit to determine which counter to use.
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@xxxxxxxxxx>
Fixes: 4e88a8621301 ("MIPS: Add cases for CPU_I6400")
Fixes: fd716fca10fc ("MIPS: perf: Fix I6400 event numbers")
Cc: linux-mips@xxxxxxxxxxxxxx
Patchwork: https://patchwork.linux-mips.org/patch/15991/
Signed-off-by: Ralf Baechle <ralf@xxxxxxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
arch/mips/kernel/perf_event_mipsxx.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -1606,7 +1606,6 @@ static const struct mips_perf_event *mip
#endif
break;
case CPU_P5600:
- case CPU_I6400:
/* 8-bit event numbers */
raw_id = config & 0x1ff;
base_id = raw_id & 0xff;
@@ -1619,6 +1618,11 @@ static const struct mips_perf_event *mip
raw_event.range = P;
#endif
break;
+ case CPU_I6400:
+ /* 8-bit event numbers */
+ base_id = config & 0xff;
+ raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
+ break;
case CPU_1004K:
if (IS_BOTH_COUNTERS_1004K_EVENT(base_id))
raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
Patches currently in stable-queue which might be from marcin.nowakowski@xxxxxxxx are
queue-4.4/mips-perf-remove-incorrect-odd-even-counter-handling-for-i6400.patch
