From: Florian Fainelli <f.fainelli@xxxxxxxxx>
commit c130d2fd3d59fbd5d269f7d5827bd4ed1d94aec6 upstream.
BMIPS5000 and BMIPS52000 processors have their I-cache filling from the
D-cache. Since BMIPS_GENERIC does not provide (yet) a
cpu-feature-overrides.h file, this was not set anywhere, so make sure
the R4K cache detection takes care of that.
Fixes: d74b0172e4e2c ("MIPS: BMIPS: Add special cache handling in c-r4k.c")
Signed-off-by: Florian Fainelli <f.fainelli@xxxxxxxxx>
Cc: linux-mips@xxxxxxxxxxxxxx
Patchwork: https://patchwork.linux-mips.org/patch/13010/
Signed-off-by: Ralf Baechle <ralf@xxxxxxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
arch/mips/mm/c-r4k.c | 4 ++++
1 file changed, 4 insertions(+)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1308,6 +1308,10 @@ static void probe_pcache(void)
c->icache.flags |= MIPS_CACHE_IC_F_DC;
break;
+ case CPU_BMIPS5000:
+ c->icache.flags |= MIPS_CACHE_IC_F_DC;
+ break;
+
case CPU_LOONGSON2:
/*
* LOONGSON2 has 4 way icache, but when using indexed cache op,
Patches currently in stable-queue which might be from f.fainelli@xxxxxxxxx are
queue-4.4/mips-bmips-adjust-mips-hpt-frequency-for-bcm7435.patch
queue-4.4/mips-bmips-clear-mips_cache_aliases-earlier.patch
queue-4.4/mips-bmips-pretty-print-bmips5200-processor-name.patch
queue-4.4/mips-bmips-bmips5000-has-i-cache-filing-from-d-cache.patch
queue-4.4/mips-bmips-fix-prid_imp_bmips5000-masking-for-bmips5200.patch
queue-4.4/mips-smp-update-cpu_foreign_map-on-cpu-disable.patch
queue-4.4/mips-bmips-local_r4k___flush_cache_all-needs-to-blast-s-cache.patch
