Hi Huacai, On Wed, Oct 23, 2019 at 09:09:01AM +0800, Huacai Chen wrote: > Reviewd-by: Huacai Chen <chenhc@xxxxxxxxxx> Thanks for the review (and as has been said many times, please stop top posting). > Hi, Paul, > > I remember that the original patch has a typo "CFUCFG", and you said > that you don't want to rewrite the history to just fix a typo. But now > Rikard has found a real bug, could rewrite be possible? No - I'm still not going to rewrite history. Yes, this LLFTPREV macro is wrong but it's also never even used so it's still not a big deal. When I said I'd only consider rewriting history for a major issue I meant it - something would need to be seriously broken for me to consider it, and even then I'm not promising I'd actually do it. Thanks, Paul > Huacai > > On Wed, Oct 23, 2019 at 3:26 AM Rikard Falkeborn > <rikard.falkeborn@xxxxxxxxx> wrote: > > > > Arguments are supposed to be ordered high then low. > > > > Fixes: 6a6f9b7dafd50efc1b2 ("MIPS: Loongson: Add CFUCFG&CSR support") > > Signed-off-by: Rikard Falkeborn <rikard.falkeborn@xxxxxxxxx> > > --- > > arch/mips/include/asm/mach-loongson64/loongson_regs.h | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/arch/mips/include/asm/mach-loongson64/loongson_regs.h b/arch/mips/include/asm/mach-loongson64/loongson_regs.h > > index 6e3569ab8936..363a47a5d26e 100644 > > --- a/arch/mips/include/asm/mach-loongson64/loongson_regs.h > > +++ b/arch/mips/include/asm/mach-loongson64/loongson_regs.h > > @@ -86,7 +86,7 @@ static inline u32 read_cpucfg(u32 reg) > > #define LOONGSON_CFG2_LGFTP BIT(19) > > #define LOONGSON_CFG2_LGFTPREV GENMASK(22, 20) > > #define LOONGSON_CFG2_LLFTP BIT(23) > > -#define LOONGSON_CFG2_LLFTPREV GENMASK(24, 26) > > +#define LOONGSON_CFG2_LLFTPREV GENMASK(26, 24) > > #define LOONGSON_CFG2_LCSRP BIT(27) > > #define LOONGSON_CFG2_LDISBLIKELY BIT(28) > > > > -- > > 2.23.0 > >