Re: [PATCH] MIPS: Loongson, workaround ll/sc weak ordering

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Hi YungQiang,

On Fri, Dec 14, 2018 at 09:50:36AM -0800, Paul Burton wrote:
> > diff --git a/arch/mips/Makefile b/arch/mips/Makefile
> > index b6303e48d..360ee1c30 100644
> > --- a/arch/mips/Makefile
> > +++ b/arch/mips/Makefile
> > @@ -194,6 +194,11 @@ cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon
> >  endif
> >  cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1
> >  cflags-$(CONFIG_CPU_BMIPS)	+= -march=mips32 -Wa,-mips32 -Wa,--trap
> > +ifeq ($(CONFIG_CPU_LOONGSON3),y)
> > +cflags-y	+= $(call cc-option,-mfix-loongson3-llsc,)
> > +else
> > +cflags-y	+= $(call cc-option,-mno-fix-loongson3-llsc,)
> > +endif
> 
> The fix-loongson3-llsc option will be default, right? At least for

erm... "will be disabled by default, right?"

/me drinks more coffee

> everything other than -march=octeon3. As such the above should just be:
> 
> cflags-$(CONFIG_CPU_LOONGSON3) += $(call cc-option,-mfix-loongson3-llsc,)
> 
> Or possibly, if we decide that we only want to support loongson3 kernels
> built with a compiler that supports this which it seems may make sense,
> it could just be:
> 
> cflags-$(CONFIG_CPU_LOONGSON3) += -mfix-loongson3-llsc

Thanks,
    Paul


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