Re: [PATCH V5 8/8] MIPS: Loongson: Introduce and use WAR_LLSC_MB

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Hi Yunqiang,

Please send only plain text mail to the linux-mips mailing list, and
don't top-post.

On Wed, Nov 28, 2018 at 08:42:08AM -0800, Yunqiang Su wrote:
> > 在 2018年11月15日,下午3:53,Huacai Chen <chenhc@xxxxxxxxxx> 写道:
> >
> > On the Loongson-2G/2H/3A/3B there is a hardware flaw that ll/sc and
> > lld/scd is very weak ordering. We should add sync instructions before
> > each ll/lld and after the last sc/scd to workaround. Otherwise, this
> > flaw will cause deadlock occationally (e.g. when doing heavy load test
> > with LTP).
> >
> > This patch is not a minimal change (it is very difficult to make a
> > minimal change), but it is a safest change.
> >
> > Why disable fix-loongson3-llsc in compiler?
> > Because compiler fix will cause problems in kernel's .fixup section.
>
> @Paul Burton Loongson 3A/B 3000 have a bug of ll/sc, which is not in 3A/3B 1000
> even.

Do you have any details? Are you saying that the problem Huacai's patch
addresses only applies to those models, or that there's a separate
problem?

Thanks,
    Paul

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