Hello,
Paul Burton wrote:
> The current methods for obtaining FP context via ptrace only provide
> either 32 or 64 bits per data register. With MSA, where vector registers
> are aliased with scalar FP data registers, those registers are 128 bits
> wide. Thus a new mechanism is required for userland to access those
> registers via ptrace. This patch introduces an NT_MIPS_MSA regset which
> provides, in this order:
>
> - The full 128 bits value of each vector register, in native
> endianness saved as though elements are doubles. That is, the format
> of each vector register is as would be obtained by saving it to
> memory using an st.d instruction.
>
> - The 32 bit scalar FP implementation register (FIR).
>
> - The 32 bit scalar FP control & status register (FCSR).
>
> - The 32 bit MSA implementation register (MSAIR).
>
> - The 32 bit MSA control & status register (MSACSR).
>
> The provision of the FIR & FCSR registers in addition to the MSA
> equivalents allows scalar FP context to be retrieved as a subset of
> the context available via this regset. Along with the MSA equivalents
> they also nicely form the final 128 bit "register" of the regset.
>
> Signed-off-by: Paul Burton <paul.burton@xxxxxxxx>
Applied to mips-next.
Thanks,
Paul
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