Hello,
Paul Burton wrote:
> The Intel EG20T Platform Controller Hub used on the MIPS Boston
> development board supports prefetching memory to optimize DMA transfers.
> Unfortunately for unknown reasons this doesn't work well with some MIPS
> CPUs such as the P6600, particularly when using an I/O Coherence Unit
> (IOCU) to provide cache-coherent DMA. In these systems it is common for
> DMA data to be lost, resulting in broken access to EG20T devices such as
> the MMC or SATA controllers.
>
> Support for a DT property to configure the prefetching was added a while
> back by commit 549ce8f134bd ("misc: pch_phub: Read prefetch value from
> device tree if passed") but we never added the DT snippet to make use of
> it. Add that now in order to disable the prefetching & fix DMA on the
> affected systems.
>
> Signed-off-by: Paul Burton <paul.burton@xxxxxxxx>
Applied to mips-next.
Thanks,
Paul
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