H Maciej, > > Set the regular and coherent DMA masks for TURBOchannel devices then, > > observing that the bus protocol supports a 34-bit (16GiB) DMA address > > space, by interpreting the value presented in the address cycle across > > the 32 `ad' lines as a 32-bit word rather than byte address[1]. The > > architectural size of the TURBOchannel DMA address space exceeds the > > maximum amount of RAM any actual TURBOchannel system in existence may > > have, hence both masks are the same. > > A complication with the PS2 OHCI is that DMA addresses 0-0x200000 map to > 0x1c000000-0x1c200000 as seen by the kernel. Robin suggested that the mask > might correspond to the effective addressing capability, which would be > DMA_BIT_MASK(21), but it does not seem to be entirely clear, since his > commit message said that > > A somewhat similar line of reasoning also applies at the other end for > the mask check in dma_alloc_attrs() too - indeed, a device which cannot > access anything other than its own local memory probably *shouldn't* > have a valid mask for the general coherent DMA API. > > A special circumstance here is the use of HCD_LOCAL_MEM that is a kind of > DMA bounce buffer. Are you using anything similar with your DEFTA driver? Sorry, I didn't interpret your comment properly. With TURBOchannel DMA address space exceeding any practical amount of RAM, bounce buffers isn't needed for that system. The situation is the reverse with the PS2 OHCI. Fredrik
