tree: https://git.kernel.org/pub/scm/linux/kernel/git/mips/linux.git mips-fixes head: f41f5d3b507ac6a18a63d948d3594952b294b43a commit: f41f5d3b507ac6a18a63d948d3594952b294b43a [1/1] MIPS: VDSO: Always map near top of user memory config: mips-allnoconfig (attached as .config) compiler: mips-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross git checkout f41f5d3b507ac6a18a63d948d3594952b294b43a # save the attached .config to linux build tree GCC_VERSION=7.2.0 make.cross ARCH=mips All error/warnings (new ones prefixed by >>): In file included from arch/mips/kernel/process.c:43:0: >> arch/mips/include/asm/mips-gic.h:12:3: error: #error Please include asm/mips-cps.h rather than asm/mips-gic.h # error Please include asm/mips-cps.h rather than asm/mips-gic.h ^~~~~ >> arch/mips/include/asm/mips-gic.h:168:17: error: expected ')' before numeric constant GIC_ACCESSOR_RW(32, 0x000, config) ^ arch/mips/include/asm/mips-gic.h:39:23: note: in definition of macro 'GIC_ACCESSOR_RW' CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_SHARED_OFS + off, name) ^~ arch/mips/include/asm/mips-gic.h: In function 'read_gic_pol': >> arch/mips/include/asm/mips-gic.h:98:23: error: implicit declaration of function 'addr_gic_pol'; did you mean 'read_gic_pol'? [-Werror=implicit-function-declaration] void __iomem *addr = addr_gic_##name(); \ ^ >> arch/mips/include/asm/mips-gic.h:114:2: note: in expansion of macro 'GIC_ACCESSOR_RO_INTR_BIT' GIC_ACCESSOR_RO_INTR_BIT(off, name) \ ^~~~~~~~~~~~~~~~~~~~~~~~ >> arch/mips/include/asm/mips-gic.h:180:1: note: in expansion of macro 'GIC_ACCESSOR_RW_INTR_BIT' GIC_ACCESSOR_RW_INTR_BIT(0x100, pol) ^~~~~~~~~~~~~~~~~~~~~~~~ >> arch/mips/include/asm/mips-gic.h:98:23: error: initialization makes pointer from integer without a cast [-Werror=int-conversion] void __iomem *addr = addr_gic_##name(); \ ^ >> arch/mips/include/asm/mips-gic.h:114:2: note: in expansion of macro 'GIC_ACCESSOR_RO_INTR_BIT' GIC_ACCESSOR_RO_INTR_BIT(off, name) \ ^~~~~~~~~~~~~~~~~~~~~~~~ >> arch/mips/include/asm/mips-gic.h:180:1: note: in expansion of macro 'GIC_ACCESSOR_RW_INTR_BIT' GIC_ACCESSOR_RW_INTR_BIT(0x100, pol) ^~~~~~~~~~~~~~~~~~~~~~~~ >> arch/mips/include/asm/mips-gic.h:101:6: error: 'mips_cm_is64' undeclared (first use in this function); did you mean 'mips_hi16'? if (mips_cm_is64) { \ ^ >> arch/mips/include/asm/mips-gic.h:114:2: note: in expansion of macro 'GIC_ACCESSOR_RO_INTR_BIT' GIC_ACCESSOR_RO_INTR_BIT(off, name) \ ^~~~~~~~~~~~~~~~~~~~~~~~ >> arch/mips/include/asm/mips-gic.h:180:1: note: in expansion of macro 'GIC_ACCESSOR_RW_INTR_BIT' GIC_ACCESSOR_RW_INTR_BIT(0x100, pol) ^~~~~~~~~~~~~~~~~~~~~~~~ arch/mips/include/asm/mips-gic.h:101:6: note: each undeclared identifier is reported only once for each function it appears in if (mips_cm_is64) { \ ^ >> arch/mips/include/asm/mips-gic.h:114:2: note: in expansion of macro 'GIC_ACCESSOR_RO_INTR_BIT' GIC_ACCESSOR_RO_INTR_BIT(off, name) \ ^~~~~~~~~~~~~~~~~~~~~~~~ >> arch/mips/include/asm/mips-gic.h:180:1: note: in expansion of macro 'GIC_ACCESSOR_RW_INTR_BIT' GIC_ACCESSOR_RW_INTR_BIT(0x100, pol) ^~~~~~~~~~~~~~~~~~~~~~~~ arch/mips/include/asm/mips-gic.h: In function 'write_gic_pol': arch/mips/include/asm/mips-gic.h:118:23: error: initialization makes pointer from integer without a cast [-Werror=int-conversion] void __iomem *addr = addr_gic_##name(); \ ^ >> arch/mips/include/asm/mips-gic.h:180:1: note: in expansion of macro 'GIC_ACCESSOR_RW_INTR_BIT' GIC_ACCESSOR_RW_INTR_BIT(0x100, pol) ^~~~~~~~~~~~~~~~~~~~~~~~ arch/mips/include/asm/mips-gic.h:120:6: error: 'mips_cm_is64' undeclared (first use in this function); did you mean 'mips_hi16'? if (mips_cm_is64) { \ ^ >> arch/mips/include/asm/mips-gic.h:180:1: note: in expansion of macro 'GIC_ACCESSOR_RW_INTR_BIT' GIC_ACCESSOR_RW_INTR_BIT(0x100, pol) ^~~~~~~~~~~~~~~~~~~~~~~~ arch/mips/include/asm/mips-gic.h: In function 'change_gic_pol': arch/mips/include/asm/mips-gic.h:132:23: error: initialization makes pointer from integer without a cast [-Werror=int-conversion] void __iomem *addr = addr_gic_##name(); \ ^ >> arch/mips/include/asm/mips-gic.h:180:1: note: in expansion of macro 'GIC_ACCESSOR_RW_INTR_BIT' GIC_ACCESSOR_RW_INTR_BIT(0x100, pol) ^~~~~~~~~~~~~~~~~~~~~~~~ arch/mips/include/asm/mips-gic.h:134:6: error: 'mips_cm_is64' undeclared (first use in this function); did you mean 'mips_hi16'? if (mips_cm_is64) { \ ^ >> arch/mips/include/asm/mips-gic.h:180:1: note: in expansion of macro 'GIC_ACCESSOR_RW_INTR_BIT' GIC_ACCESSOR_RW_INTR_BIT(0x100, pol) ^~~~~~~~~~~~~~~~~~~~~~~~ arch/mips/include/asm/mips-gic.h: In function 'read_gic_trig': >> arch/mips/include/asm/mips-gic.h:101:6: error: 'mips_cm_is64' undeclared (first use in this function); did you mean 'mips_hi16'? if (mips_cm_is64) { \ ^ >> arch/mips/include/asm/mips-gic.h:114:2: note: in expansion of macro 'GIC_ACCESSOR_RO_INTR_BIT' GIC_ACCESSOR_RO_INTR_BIT(off, name) \ ^~~~~~~~~~~~~~~~~~~~~~~~ arch/mips/include/asm/mips-gic.h:187:1: note: in expansion of macro 'GIC_ACCESSOR_RW_INTR_BIT' GIC_ACCESSOR_RW_INTR_BIT(0x180, trig) ^~~~~~~~~~~~~~~~~~~~~~~~ arch/mips/include/asm/mips-gic.h: In function 'write_gic_trig': arch/mips/include/asm/mips-gic.h:120:6: error: 'mips_cm_is64' undeclared (first use in this function); did you mean 'mips_hi16'? if (mips_cm_is64) { \ ^ arch/mips/include/asm/mips-gic.h:187:1: note: in expansion of macro 'GIC_ACCESSOR_RW_INTR_BIT' GIC_ACCESSOR_RW_INTR_BIT(0x180, trig) ^~~~~~~~~~~~~~~~~~~~~~~~ arch/mips/include/asm/mips-gic.h: In function 'change_gic_trig': arch/mips/include/asm/mips-gic.h:134:6: error: 'mips_cm_is64' undeclared (first use in this function); did you mean 'mips_hi16'? if (mips_cm_is64) { \ ^ arch/mips/include/asm/mips-gic.h:187:1: note: in expansion of macro 'GIC_ACCESSOR_RW_INTR_BIT' GIC_ACCESSOR_RW_INTR_BIT(0x180, trig) ^~~~~~~~~~~~~~~~~~~~~~~~ arch/mips/include/asm/mips-gic.h: In function 'read_gic_dual': >> arch/mips/include/asm/mips-gic.h:101:6: error: 'mips_cm_is64' undeclared (first use in this function); did you mean 'mips_hi16'? if (mips_cm_is64) { \ ^ vim +12 arch/mips/include/asm/mips-gic.h 582e2b4a Paul Burton 2017-08-12 @12 # error Please include asm/mips-cps.h rather than asm/mips-gic.h 582e2b4a Paul Burton 2017-08-12 13 #endif 582e2b4a Paul Burton 2017-08-12 14 582e2b4a Paul Burton 2017-08-12 15 #ifndef __MIPS_ASM_MIPS_GIC_H__ 582e2b4a Paul Burton 2017-08-12 16 #define __MIPS_ASM_MIPS_GIC_H__ 582e2b4a Paul Burton 2017-08-12 17 582e2b4a Paul Burton 2017-08-12 18 #include <linux/bitops.h> 582e2b4a Paul Burton 2017-08-12 19 582e2b4a Paul Burton 2017-08-12 20 /* The base address of the GIC registers */ 582e2b4a Paul Burton 2017-08-12 21 extern void __iomem *mips_gic_base; 582e2b4a Paul Burton 2017-08-12 22 582e2b4a Paul Burton 2017-08-12 23 /* Offsets from the GIC base address to various control blocks */ 582e2b4a Paul Burton 2017-08-12 24 #define MIPS_GIC_SHARED_OFS 0x00000 582e2b4a Paul Burton 2017-08-12 25 #define MIPS_GIC_SHARED_SZ 0x08000 582e2b4a Paul Burton 2017-08-12 26 #define MIPS_GIC_LOCAL_OFS 0x08000 582e2b4a Paul Burton 2017-08-12 27 #define MIPS_GIC_LOCAL_SZ 0x04000 582e2b4a Paul Burton 2017-08-12 28 #define MIPS_GIC_REDIR_OFS 0x0c000 582e2b4a Paul Burton 2017-08-12 29 #define MIPS_GIC_REDIR_SZ 0x04000 582e2b4a Paul Burton 2017-08-12 30 #define MIPS_GIC_USER_OFS 0x10000 582e2b4a Paul Burton 2017-08-12 31 #define MIPS_GIC_USER_SZ 0x10000 582e2b4a Paul Burton 2017-08-12 32 582e2b4a Paul Burton 2017-08-12 33 /* For read-only shared registers */ 582e2b4a Paul Burton 2017-08-12 34 #define GIC_ACCESSOR_RO(sz, off, name) \ 582e2b4a Paul Burton 2017-08-12 35 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_SHARED_OFS + off, name) 582e2b4a Paul Burton 2017-08-12 36 582e2b4a Paul Burton 2017-08-12 37 /* For read-write shared registers */ 582e2b4a Paul Burton 2017-08-12 38 #define GIC_ACCESSOR_RW(sz, off, name) \ 582e2b4a Paul Burton 2017-08-12 @39 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_SHARED_OFS + off, name) 582e2b4a Paul Burton 2017-08-12 40 582e2b4a Paul Burton 2017-08-12 41 /* For read-only local registers */ 582e2b4a Paul Burton 2017-08-12 42 #define GIC_VX_ACCESSOR_RO(sz, off, name) \ 582e2b4a Paul Burton 2017-08-12 43 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_LOCAL_OFS + off, vl_##name) \ 582e2b4a Paul Burton 2017-08-12 44 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name) 582e2b4a Paul Burton 2017-08-12 45 582e2b4a Paul Burton 2017-08-12 46 /* For read-write local registers */ 582e2b4a Paul Burton 2017-08-12 47 #define GIC_VX_ACCESSOR_RW(sz, off, name) \ 582e2b4a Paul Burton 2017-08-12 @48 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_LOCAL_OFS + off, vl_##name) \ 582e2b4a Paul Burton 2017-08-12 49 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name) 582e2b4a Paul Burton 2017-08-12 50 582e2b4a Paul Burton 2017-08-12 51 /* For read-only shared per-interrupt registers */ 582e2b4a Paul Burton 2017-08-12 52 #define GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \ 582e2b4a Paul Burton 2017-08-12 53 static inline void __iomem *addr_gic_##name(unsigned int intr) \ 582e2b4a Paul Burton 2017-08-12 54 { \ 582e2b4a Paul Burton 2017-08-12 55 return mips_gic_base + (off) + (intr * (stride)); \ 582e2b4a Paul Burton 2017-08-12 56 } \ 582e2b4a Paul Burton 2017-08-12 57 \ 582e2b4a Paul Burton 2017-08-12 58 static inline unsigned int read_gic_##name(unsigned int intr) \ 582e2b4a Paul Burton 2017-08-12 59 { \ 582e2b4a Paul Burton 2017-08-12 60 BUILD_BUG_ON(sz != 32); \ 582e2b4a Paul Burton 2017-08-12 @61 return __raw_readl(addr_gic_##name(intr)); \ 582e2b4a Paul Burton 2017-08-12 62 } 582e2b4a Paul Burton 2017-08-12 63 582e2b4a Paul Burton 2017-08-12 64 /* For read-write shared per-interrupt registers */ 582e2b4a Paul Burton 2017-08-12 65 #define GIC_ACCESSOR_RW_INTR_REG(sz, off, stride, name) \ 582e2b4a Paul Burton 2017-08-12 @66 GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \ 582e2b4a Paul Burton 2017-08-12 67 \ 582e2b4a Paul Burton 2017-08-12 68 static inline void write_gic_##name(unsigned int intr, \ 582e2b4a Paul Burton 2017-08-12 69 unsigned int val) \ 582e2b4a Paul Burton 2017-08-12 70 { \ 582e2b4a Paul Burton 2017-08-12 71 BUILD_BUG_ON(sz != 32); \ 582e2b4a Paul Burton 2017-08-12 @72 __raw_writel(val, addr_gic_##name(intr)); \ 582e2b4a Paul Burton 2017-08-12 73 } 582e2b4a Paul Burton 2017-08-12 74 582e2b4a Paul Burton 2017-08-12 75 /* For read-only local per-interrupt registers */ 582e2b4a Paul Burton 2017-08-12 76 #define GIC_VX_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \ 582e2b4a Paul Burton 2017-08-12 77 GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_LOCAL_OFS + off, \ 582e2b4a Paul Burton 2017-08-12 78 stride, vl_##name) \ 582e2b4a Paul Burton 2017-08-12 79 GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off, \ 582e2b4a Paul Burton 2017-08-12 80 stride, vo_##name) 582e2b4a Paul Burton 2017-08-12 81 582e2b4a Paul Burton 2017-08-12 82 /* For read-write local per-interrupt registers */ 582e2b4a Paul Burton 2017-08-12 83 #define GIC_VX_ACCESSOR_RW_INTR_REG(sz, off, stride, name) \ 582e2b4a Paul Burton 2017-08-12 @84 GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_LOCAL_OFS + off, \ 582e2b4a Paul Burton 2017-08-12 85 stride, vl_##name) \ 582e2b4a Paul Burton 2017-08-12 86 GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off, \ 582e2b4a Paul Burton 2017-08-12 87 stride, vo_##name) 582e2b4a Paul Burton 2017-08-12 88 582e2b4a Paul Burton 2017-08-12 89 /* For read-only shared bit-per-interrupt registers */ 582e2b4a Paul Burton 2017-08-12 90 #define GIC_ACCESSOR_RO_INTR_BIT(off, name) \ 582e2b4a Paul Burton 2017-08-12 91 static inline void __iomem *addr_gic_##name(void) \ 582e2b4a Paul Burton 2017-08-12 92 { \ 582e2b4a Paul Burton 2017-08-12 93 return mips_gic_base + (off); \ 582e2b4a Paul Burton 2017-08-12 94 } \ 582e2b4a Paul Burton 2017-08-12 95 \ 582e2b4a Paul Burton 2017-08-12 96 static inline unsigned int read_gic_##name(unsigned int intr) \ 582e2b4a Paul Burton 2017-08-12 97 { \ 582e2b4a Paul Burton 2017-08-12 @98 void __iomem *addr = addr_gic_##name(); \ 582e2b4a Paul Burton 2017-08-12 99 unsigned int val; \ 582e2b4a Paul Burton 2017-08-12 100 \ 582e2b4a Paul Burton 2017-08-12 @101 if (mips_cm_is64) { \ 582e2b4a Paul Burton 2017-08-12 102 addr += (intr / 64) * sizeof(uint64_t); \ 582e2b4a Paul Burton 2017-08-12 103 val = __raw_readq(addr) >> intr % 64; \ 582e2b4a Paul Burton 2017-08-12 104 } else { \ 582e2b4a Paul Burton 2017-08-12 105 addr += (intr / 32) * sizeof(uint32_t); \ 582e2b4a Paul Burton 2017-08-12 106 val = __raw_readl(addr) >> intr % 32; \ 582e2b4a Paul Burton 2017-08-12 107 } \ 582e2b4a Paul Burton 2017-08-12 108 \ 582e2b4a Paul Burton 2017-08-12 109 return val & 0x1; \ 582e2b4a Paul Burton 2017-08-12 110 } 582e2b4a Paul Burton 2017-08-12 111 582e2b4a Paul Burton 2017-08-12 112 /* For read-write shared bit-per-interrupt registers */ 582e2b4a Paul Burton 2017-08-12 113 #define GIC_ACCESSOR_RW_INTR_BIT(off, name) \ 582e2b4a Paul Burton 2017-08-12 @114 GIC_ACCESSOR_RO_INTR_BIT(off, name) \ 582e2b4a Paul Burton 2017-08-12 115 \ 582e2b4a Paul Burton 2017-08-12 116 static inline void write_gic_##name(unsigned int intr) \ 582e2b4a Paul Burton 2017-08-12 117 { \ 582e2b4a Paul Burton 2017-08-12 118 void __iomem *addr = addr_gic_##name(); \ 582e2b4a Paul Burton 2017-08-12 119 \ 582e2b4a Paul Burton 2017-08-12 120 if (mips_cm_is64) { \ 582e2b4a Paul Burton 2017-08-12 121 addr += (intr / 64) * sizeof(uint64_t); \ 582e2b4a Paul Burton 2017-08-12 122 __raw_writeq(BIT(intr % 64), addr); \ 582e2b4a Paul Burton 2017-08-12 123 } else { \ 582e2b4a Paul Burton 2017-08-12 124 addr += (intr / 32) * sizeof(uint32_t); \ 582e2b4a Paul Burton 2017-08-12 125 __raw_writel(BIT(intr % 32), addr); \ 582e2b4a Paul Burton 2017-08-12 126 } \ 582e2b4a Paul Burton 2017-08-12 127 } \ 582e2b4a Paul Burton 2017-08-12 128 \ 582e2b4a Paul Burton 2017-08-12 129 static inline void change_gic_##name(unsigned int intr, \ 582e2b4a Paul Burton 2017-08-12 130 unsigned int val) \ 582e2b4a Paul Burton 2017-08-12 131 { \ 582e2b4a Paul Burton 2017-08-12 132 void __iomem *addr = addr_gic_##name(); \ 582e2b4a Paul Burton 2017-08-12 133 \ 582e2b4a Paul Burton 2017-08-12 134 if (mips_cm_is64) { \ 582e2b4a Paul Burton 2017-08-12 135 uint64_t _val; \ 582e2b4a Paul Burton 2017-08-12 136 \ 582e2b4a Paul Burton 2017-08-12 137 addr += (intr / 64) * sizeof(uint64_t); \ 582e2b4a Paul Burton 2017-08-12 138 _val = __raw_readq(addr); \ 582e2b4a Paul Burton 2017-08-12 139 _val &= ~BIT_ULL(intr % 64); \ 582e2b4a Paul Burton 2017-08-12 140 _val |= (uint64_t)val << (intr % 64); \ 582e2b4a Paul Burton 2017-08-12 141 __raw_writeq(_val, addr); \ 582e2b4a Paul Burton 2017-08-12 142 } else { \ 582e2b4a Paul Burton 2017-08-12 143 uint32_t _val; \ 582e2b4a Paul Burton 2017-08-12 144 \ 582e2b4a Paul Burton 2017-08-12 145 addr += (intr / 32) * sizeof(uint32_t); \ 582e2b4a Paul Burton 2017-08-12 146 _val = __raw_readl(addr); \ 582e2b4a Paul Burton 2017-08-12 147 _val &= ~BIT(intr % 32); \ 582e2b4a Paul Burton 2017-08-12 148 _val |= val << (intr % 32); \ 582e2b4a Paul Burton 2017-08-12 149 __raw_writel(_val, addr); \ 582e2b4a Paul Burton 2017-08-12 150 } \ 582e2b4a Paul Burton 2017-08-12 151 } 582e2b4a Paul Burton 2017-08-12 152 582e2b4a Paul Burton 2017-08-12 153 /* For read-only local bit-per-interrupt registers */ 582e2b4a Paul Burton 2017-08-12 154 #define GIC_VX_ACCESSOR_RO_INTR_BIT(sz, off, name) \ 582e2b4a Paul Burton 2017-08-12 155 GIC_ACCESSOR_RO_INTR_BIT(sz, MIPS_GIC_LOCAL_OFS + off, \ 582e2b4a Paul Burton 2017-08-12 156 vl_##name) \ 582e2b4a Paul Burton 2017-08-12 157 GIC_ACCESSOR_RO_INTR_BIT(sz, MIPS_GIC_REDIR_OFS + off, \ 582e2b4a Paul Burton 2017-08-12 158 vo_##name) 582e2b4a Paul Burton 2017-08-12 159 582e2b4a Paul Burton 2017-08-12 160 /* For read-write local bit-per-interrupt registers */ 582e2b4a Paul Burton 2017-08-12 161 #define GIC_VX_ACCESSOR_RW_INTR_BIT(sz, off, name) \ 582e2b4a Paul Burton 2017-08-12 162 GIC_ACCESSOR_RW_INTR_BIT(sz, MIPS_GIC_LOCAL_OFS + off, \ 582e2b4a Paul Burton 2017-08-12 163 vl_##name) \ 582e2b4a Paul Burton 2017-08-12 164 GIC_ACCESSOR_RW_INTR_BIT(sz, MIPS_GIC_REDIR_OFS + off, \ 582e2b4a Paul Burton 2017-08-12 165 vo_##name) 582e2b4a Paul Burton 2017-08-12 166 582e2b4a Paul Burton 2017-08-12 167 /* GIC_SH_CONFIG - Information about the GIC configuration */ 582e2b4a Paul Burton 2017-08-12 @168 GIC_ACCESSOR_RW(32, 0x000, config) 582e2b4a Paul Burton 2017-08-12 169 #define GIC_CONFIG_COUNTSTOP BIT(28) 582e2b4a Paul Burton 2017-08-12 170 #define GIC_CONFIG_COUNTBITS GENMASK(27, 24) 582e2b4a Paul Burton 2017-08-12 171 #define GIC_CONFIG_NUMINTERRUPTS GENMASK(23, 16) 582e2b4a Paul Burton 2017-08-12 172 #define GIC_CONFIG_PVPS GENMASK(6, 0) 582e2b4a Paul Burton 2017-08-12 173 582e2b4a Paul Burton 2017-08-12 174 /* GIC_SH_COUNTER - Shared global counter value */ 582e2b4a Paul Burton 2017-08-12 175 GIC_ACCESSOR_RW(64, 0x010, counter) 582e2b4a Paul Burton 2017-08-12 176 GIC_ACCESSOR_RW(32, 0x010, counter_32l) 582e2b4a Paul Burton 2017-08-12 177 GIC_ACCESSOR_RW(32, 0x014, counter_32h) 582e2b4a Paul Burton 2017-08-12 178 582e2b4a Paul Burton 2017-08-12 179 /* GIC_SH_POL_* - Configures interrupt polarity */ 582e2b4a Paul Burton 2017-08-12 @180 GIC_ACCESSOR_RW_INTR_BIT(0x100, pol) 582e2b4a Paul Burton 2017-08-12 181 #define GIC_POL_ACTIVE_LOW 0 /* when level triggered */ 582e2b4a Paul Burton 2017-08-12 182 #define GIC_POL_ACTIVE_HIGH 1 /* when level triggered */ 582e2b4a Paul Burton 2017-08-12 183 #define GIC_POL_FALLING_EDGE 0 /* when single-edge triggered */ 582e2b4a Paul Burton 2017-08-12 184 #define GIC_POL_RISING_EDGE 1 /* when single-edge triggered */ 582e2b4a Paul Burton 2017-08-12 185 582e2b4a Paul Burton 2017-08-12 186 /* GIC_SH_TRIG_* - Configures interrupts to be edge or level triggered */ 582e2b4a Paul Burton 2017-08-12 187 GIC_ACCESSOR_RW_INTR_BIT(0x180, trig) 582e2b4a Paul Burton 2017-08-12 188 #define GIC_TRIG_LEVEL 0 582e2b4a Paul Burton 2017-08-12 189 #define GIC_TRIG_EDGE 1 582e2b4a Paul Burton 2017-08-12 190 582e2b4a Paul Burton 2017-08-12 191 /* GIC_SH_DUAL_* - Configures whether interrupts trigger on both edges */ 582e2b4a Paul Burton 2017-08-12 192 GIC_ACCESSOR_RW_INTR_BIT(0x200, dual) 582e2b4a Paul Burton 2017-08-12 193 #define GIC_DUAL_SINGLE 0 /* when edge-triggered */ 582e2b4a Paul Burton 2017-08-12 194 #define GIC_DUAL_DUAL 1 /* when edge-triggered */ 582e2b4a Paul Burton 2017-08-12 195 582e2b4a Paul Burton 2017-08-12 196 /* GIC_SH_WEDGE - Write an 'edge', ie. trigger an interrupt */ 582e2b4a Paul Burton 2017-08-12 @197 GIC_ACCESSOR_RW(32, 0x280, wedge) 582e2b4a Paul Burton 2017-08-12 198 #define GIC_WEDGE_RW BIT(31) 582e2b4a Paul Burton 2017-08-12 199 #define GIC_WEDGE_INTR GENMASK(7, 0) 582e2b4a Paul Burton 2017-08-12 200 :::::: The code at line 12 was first introduced by commit :::::: 582e2b4aecdacc0a3bd39daa63648a88cad6a26f MIPS: GIC: Introduce asm/mips-gic.h with accessor functions :::::: TO: Paul Burton <paul.burton@xxxxxxxxxx> :::::: CC: Ralf Baechle <ralf@xxxxxxxxxxxxxx> --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
Attachment:
.config.gz
Description: application/gzip
