Hi Paul, On Wed, 2018-09-26 at 22:18 +0000, Paul Burton wrote: > Hi Yasha, > > On Wed, Sep 26, 2018 at 02:16:15PM +0300, Yasha Cherikovsky wrote: > > MIPSR6 CPUs do not support unaligned load/store instructions > > (LWL, LWR, SWL, SWR and LDL, LDR, SDL, SDR for 64bit). > > > > Currently the MIPS tree has some special cases to avoid these > > instructions, and the code is testing for !CONFIG_CPU_MIPSR6. > > > > This patch declares a new Kconfig variable: > > CONFIG_CPU_HAS_LOAD_STORE_LR. > > This variable indicates that the CPU supports these instructions. > > > > Then, the patch does the following: > > - Carefully selects this option on all CPUs except MIPSR6. > > - Switches all the special cases to test for the new variable, > > and inverts the logic: > > '#ifndef CONFIG_CPU_MIPSR6' turns into > > '#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR' > > and vice-versa. > > > > Also, when this variable is NOT selected (e.g. MIPSR6), > > CONFIG_GENERIC_CSUM will default to 'y', to compile generic > > C checksum code (instead of special assembly code that uses the > > unsupported instructions). > > > > This commit should not affect any existing CPU, and is required > > for future Lexra CPU support, that misses these instructions too. > > > > Signed-off-by: Yasha Cherikovsky <yasha.che3@xxxxxxxxx> > > Cc: Ralf Baechle <ralf@xxxxxxxxxxxxxx> > > Cc: Paul Burton <paul.burton@xxxxxxxx> > > Cc: James Hogan <jhogan@xxxxxxxxxx> > > Cc: linux-mips@xxxxxxxxxxxxxx > > Cc: linux-kernel@xxxxxxxxxxxxxxx > > --- > > arch/mips/Kconfig | 35 +++++++++++++++++++++++++-- > > arch/mips/kernel/unaligned.c | 47 ++++++++++++++++++------------------ > > arch/mips/lib/memcpy.S | 10 ++++---- > > arch/mips/lib/memset.S | 12 ++++----- > > 4 files changed, 67 insertions(+), 37 deletions(-) > > Thanks - applied to mips-next for 4.20. > > Paul Thanks! Yasha
