Re: [PATCH V2 04/25] MIPS: ath79: fix register address in ath79_ddr_wb_flush()

[Paul Burton <paul.burton@xxxxxxxx>]

Hi John / Felix,

On Fri, Jul 20, 2018 at 01:58:21PM +0200, John Crispin wrote:
> diff --git a/arch/mips/ath79/common.c b/arch/mips/ath79/common.c
> index fad32543a968..cd6055f9e7a0 100644
> --- a/arch/mips/ath79/common.c
> +++ b/arch/mips/ath79/common.c
> @@ -58,7 +58,7 @@ EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init);
>  
>  void ath79_ddr_wb_flush(u32 reg)
>  {
> -	void __iomem *flush_reg = ath79_ddr_wb_flush_base + reg;
> +	void __iomem *flush_reg = ath79_ddr_wb_flush_base + (reg * 4);
>  
>  	/* Flush the DDR write buffer. */
>  	__raw_writel(0x1, flush_reg);

Thanks - I've applied this one to mips-fixes & marked for backport as
far as 4.2.

Paul