3.18-stable review patch. If anyone has any objections, please let me know. ------------------ From: Sinan Kaya <okaya@xxxxxxxxxxxxxx> [ Upstream commit a1cc7034e33d12dc17d13fbcd7d597d552889097 ] While a barrier is present in the writeX() functions before the register write, a similar barrier is missing in the readX() functions after the register read. This could allow memory accesses following readX() to observe stale data. Signed-off-by: Sinan Kaya <okaya@xxxxxxxxxxxxxx> Reported-by: Arnd Bergmann <arnd@xxxxxxxx> Cc: Ralf Baechle <ralf@xxxxxxxxxxxxxx> Cc: Paul Burton <paul.burton@xxxxxxxx> Cc: linux-mips@xxxxxxxxxxxxxx Patchwork: https://patchwork.linux-mips.org/patch/19069/ [jhogan@xxxxxxxxxx: Tidy commit message] Signed-off-by: James Hogan <jhogan@xxxxxxxxxx> Signed-off-by: Sasha Levin <alexander.levin@xxxxxxxxxxxxx> Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> --- arch/mips/include/asm/io.h | 2 ++ 1 file changed, 2 insertions(+) --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -375,6 +375,8 @@ static inline type pfx##read##bwlq(const BUG(); \ } \ \ + /* prevent prefetching of coherent DMA data prematurely */ \ + rmb(); \ return pfx##ioswab##bwlq(__mem, __val); \ }
