On 06/25/2018 08:15 PM, John Crispin wrote:
> With the driver being converted from platform_data to pure OF, we need to
> also add some docs.
>
> Cc: Rob Herring <robh+dt@xxxxxxxxxx>
> Cc: devicetree@xxxxxxxxxxxxxxx
> Signed-off-by: John Crispin <john@xxxxxxxxxxx>
> ---
> .../devicetree/bindings/pci/qcom,ar7100-pci.txt | 36 ++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt b/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt
> new file mode 100644
> index 000000000000..97be7b0c4cf9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt
> @@ -0,0 +1,36 @@
> +* Qualcomm Atheros AR7100 PCI express root complex
> +
> +Required properties:
> +- compatible: should contain "qcom,ar7100-pci" to identify the core.
> +- reg: Should contain the register ranges as listed in the reg-names property.
> +- reg-names: Definition: Must include the following entries
> + - "cfg_base" IO Memory
> +- #address-cells: set to <3>
> +- #size-cells: set to <2>
> +- ranges: ranges for the PCI memory and I/O regions
> +- interrupt-map-mask and interrupt-map: standard PCI
> + properties to define the mapping of the PCIe interface to interrupt
> + numbers.
> +- #interrupt-cells: set to <1>
> +- interrupt-parent: phandle to the MIPS IRQ controller
Never a required prop, can be "inherited" from the parent node.
> +- interrupt-controller: define to enable the builtin IRQ cascade.
> +
> +* Example for ar7100
> + pcie0: pcie-controller@180c0000 {
Name it just "pcie@180c0000", please.
[...]
MBR, Sergei
