RE: [PATCH v3 1/1] MIPS: BCM47XX: Enable MIPS32 74K Core ExternalSync for BCM47XX PCIe erratum

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Hi Paul-san,

Thank you so much for your reviewing.

> My only other niggle would be questioning whether we really need the
> pr_info() - I'd probably go without it, but it's not a strong opinion so
> either way:

  I have just sent v4 patch without pr_info().

>     Reviewed-by: Paul Burton <paul.burton@xxxxxxxx>

  Also I added this Reviewed-by tag line into the commit message.

Regards,
Ikegami

> -----Original Message-----
> From: Paul Burton [mailto:paul.burton@xxxxxxxx]
> Sent: Friday, June 01, 2018 6:06 AM
> To: IKEGAMI Tokunori
> Cc: James Hogan; PACKHAM Chris; Hauke Mehrtens; Rafał Miłecki;
> linux-mips@xxxxxxxxxxxxxx
> Subject: Re: [PATCH v3 1/1] MIPS: BCM47XX: Enable MIPS32 74K Core
> ExternalSync for BCM47XX PCIe erratum
> 
> Hi Tokunori,
> 
> On Thu, May 31, 2018 at 10:02:40AM +0900, Tokunori Ikegami wrote:
> > diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c
> > index 6054d49e608e..8fec219e1160 100644
> > --- a/arch/mips/bcm47xx/setup.c
> > +++ b/arch/mips/bcm47xx/setup.c
> > @@ -212,6 +212,13 @@ static int __init bcm47xx_cpu_fixes(void)
> >  		 */
> >  		if (bcm47xx_bus.bcma.bus.chipinfo.id ==
> BCMA_CHIP_ID_BCM4706)
> >  			cpu_wait = NULL;
> > +
> > +		/*
> > +		 * BCM47XX Erratum "R10: PCIe Transactions Periodically
> Fail"
> > +		 * Enable ExternalSync for sync instruction to take effect
> > +		 */
> > +		pr_info("ExternalSync has been enabled\n");
> > +		set_c0_config7(MIPS_CONF7_ES);
> 
> Great - this looks better placed than v2, and so long as this erratum
> only applies to systems using BCMA this looks good to me.
> 
> My only other niggle would be questioning whether we really need the
> pr_info() - I'd probably go without it, but it's not a strong opinion so
> either way:
> 
>     Reviewed-by: Paul Burton <paul.burton@xxxxxxxx>
> 
> Thanks,
>     Paul




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