Hi MIPS Maintainers, memory-barriers.txt has been updated not to require a wmb() before writel() since Linus asked all infrastructures to follow Intel paradigm where writes are ordered and they do not require a barrier between a memory update and HW observation. https://www.mail-archive.com/netdev@xxxxxxxxxxxxxxx/msg225806.html https://lkml.org/lkml/2018/3/27/431 We have been auditing all architectures to see if they follow this requirement or not. Arnd raised the following concern that MIPS would be non-compliant. Can somebody familiar with MIPS evaluate this? Sinan -- Sinan Kaya Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
