On 03/23/2018 01:11 PM, Alexandre Belloni wrote: > DT bindings for the Microsemi MII Management Controller found on Microsemi > SoCs > > Cc: Rob Herring <robh+dt@xxxxxxxxxx> > Signed-off-by: Alexandre Belloni <alexandre.belloni@xxxxxxxxxxx> > --- > .../devicetree/bindings/net/mscc-miim.txt | 25 ++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/mscc-miim.txt > > diff --git a/Documentation/devicetree/bindings/net/mscc-miim.txt b/Documentation/devicetree/bindings/net/mscc-miim.txt > new file mode 100644 > index 000000000000..711ac9ab853c > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/mscc-miim.txt > @@ -0,0 +1,25 @@ > +Microsemi MII Management Controller (MIIM) / MDIO > +================================================= > + > +Properties: > +- compatible: must be "mscc,ocelot-miim" > +- reg: The base address of the MDIO bus controller register bank. Optionally, a > + second register bank can be defined if there is an associated reset register > + for internal PHYs > +- #address-cells: Must be <1>. > +- #size-cells: Must be <0>. MDIO addresses have no size component. Missing interrupt property documentation (sorry), other than that: Reviewed-by: Florian Fainelli <f.fainelli@xxxxxxxxx> -- Florian
