Hi James,
On Mon, Mar 12, 2018 at 10:17 PM, James Hogan <jhogan@xxxxxxxxxx> wrote:
> Hi,
>
> On Sun, Mar 11, 2018 at 06:41:22PM +0100, Hauke Mehrtens wrote:
>> From: Mathias Kresin <dev@xxxxxxxxx>
>>
>> On Danube and AR9 the USB core is connected to the AHB bus, hence we need
>> to enable the AHB Bus as well.
>>
>> Fixes: dea54fbad332 ("phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module")
>> Signed-off-by: Mathias Kresin <dev@xxxxxxxxx>
>
> Hauke: I think this needs your SoB line too (same for other 2 patches
> too).
>
>> ---
>> arch/mips/lantiq/xway/sysctrl.c | 6 +++---
>> 1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
>> index f11f1dd10493..e0af39b33e28 100644
>> --- a/arch/mips/lantiq/xway/sysctrl.c
>> +++ b/arch/mips/lantiq/xway/sysctrl.c
>> @@ -549,9 +549,9 @@ void __init ltq_soc_init(void)
>> clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
>> ltq_ar9_fpi_hz(), CLOCK_250M);
>> clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
>> - clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
>> + clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM);
>
> Checkpatch complains about these changed lines all being >80 columns,
> though there are admittedly other violations nearby too.
I suggest to keep it as suggested by Mathias/Hauke.
our (Hauke and my) plan is to remove the whole file and replace it
with a driver based on the common clock framework (in drivers/clk/)
mid-term. in my opinion this is better than just fixing the 80 column
limit
Regards
Martin
