On Tue, Mar 06, 2018 at 01:16:06PM +0100, Alexandre Belloni wrote: > diff --git a/arch/mips/Makefile b/arch/mips/Makefile > index d1ca839c3981..d2882244cf1f 100644 > --- a/arch/mips/Makefile > +++ b/arch/mips/Makefile > @@ -543,6 +543,10 @@ generic_defconfig: > # now that the boards have been converted to use the generic kernel they are > # wrappers around the generic rules above. > # > +.PHONY: ocelot_defconfig > +ocelot_defconfig: > + $(Q)$(MAKE) -f $(srctree)/Makefile 32r2el_defconfig BOARDS=ocelot FYI this conflicts with https://patchwork.linux-mips.org/patch/18596/, but can be trivially fixed up when applied to the following, so no need for you to rebase: diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 2ed4c8927701..646a2d98012d 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -565,6 +565,9 @@ generic_defconfig: # now that the boards have been converted to use the generic kernel they are # wrappers around the generic rules above. # +legacy_defconfigs += ocelot_defconfig +ocelot_defconfig-y := 32r2el_defconfig BOARDS=ocelot + legacy_defconfigs += sead3_defconfig sead3_defconfig-y := 32r2el_defconfig BOARDS=sead-3 > + > .PHONY: sead3_defconfig > sead3_defconfig: > $(Q)$(MAKE) -f $(srctree)/Makefile 32r2el_defconfig BOARDS=sead-3 > diff --git a/arch/mips/configs/generic/board-ocelot.config b/arch/mips/configs/generic/board-ocelot.config > new file mode 100644 > index 000000000000..fa4e8988ebc8 > --- /dev/null > +++ b/arch/mips/configs/generic/board-ocelot.config > @@ -0,0 +1,36 @@ > +# require CONFIG_32BIT=y That should be implied now by CPU_SUPPORTS_64BIT_KERNEL=n since CONFIG_CPU_MIPS32_R2=y. > +# require CONFIG_CPU_MIPS32_R2=y > +static __init bool ocelot_detect(void) > +{ > + u32 rev; > + > + rev = __raw_readl((void *)DEVCPU_GCB_CHIP_REGS_CHIP_ID); How about a TLB check first, a bit like _kvm_mips_host_tlb_inv() in arch/mips/kvm/tlb.c, i.e.: int idx; /* Look for the TLB entry set up by redboot before trying to use it */ write_c0_entryhi(DEVCPU_GCB_CHIP_REGS_CHIP_ID); mtc0_tlbw_hazard(); tlb_probe(); tlb_probe_hazard(); idx = read_c0_index(); if (idx < 0) return 0; /* A TLB entry exists, lets assume its usable and check the CHIP ID */ rev = __raw_readl((void __iomem *)DEVCPU_GCB_CHIP_REGS_CHIP_ID); (That assumes that if a TLB entry exists that it will be usable, which isn't technically complete since the entry may not be marked valid, but its probably sufficient in practice). Incidentally you need to use __iomem there to avoid the following sparse error: arch/mips/generic/board-ocelot.c:21:28: warning: incorrect type in argument 1 (different address spaces) arch/mips/generic/board-ocelot.c:21:28: expected void const volatile [noderef] <asn:2>*mem arch/mips/generic/board-ocelot.c:21:28: got void *<noident> Cheers James
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