Hi James,
James Hogan wrote:
> From 17278a91e04f858155d54bee5528ba4fbcec6f87 Mon Sep 17 00:00:00 2001
> From: James Hogan <jhogan@xxxxxxxxxx>
> Date: Tue, 14 Nov 2017 12:01:20 +0000
> Subject: [PATCH] MIPS: CPS: Fix r1 .set mt assembler warning
>
> MIPS CPS has a build warning on kernels configured for MIPS32R1 or
> MIPS64R1, due to the use of .set mt without a prior .set mips{32,64}r2:
>
> arch/mips/kernel/cps-vec.S Assembler messages:
> arch/mips/kernel/cps-vec.S:238: Warning: the `mt' extension requires MIPS32 revision 2 or greater
>
> Add .set MIPS_ISA_LEVEL_RAW before .set mt to silence the warning.
This change breaks booting for me on a MediaTek MT7621 platform:
...
Calibrating delay loop... 586.13 BogoMIPS (lpj=2930688)^M
pid_max: default: 32768 minimum: 301^M
Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)^M
Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)^M
Hierarchical SRCU implementation.^M
smp: Bringing up secondary CPUs ...^M
Reserved instruction in kernel code[#1]:^M
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.15.0-ac0 #3^M
$ 0 : 00000000 00000001 00000000 00000000^M
$ 4 : 8501dd80 00000001 00000004 00000000^M
$ 8 : 00000004 00000002 00000001 ffffffff^M
$12 : 00000000 00000400 00000003 8501de00^M
$16 : 807d5ca0 8501dd80 00000000 00000001^M
$20 : 80842814 00000000 00000001 000000e0^M
$24 : fffffffc 00000001 ^M
$28 : 85026000 85027de0 00000020 80013538^M
Hi : 00000006^M
Lo : 8e778000^M
epc : 80656620 mips_cps_boot_vpes+0x4c/0x160^M
ra : 80013538 cps_boot_secondary+0x280/0x440^M
Status: 11000403 KERNEL EXL IE ^M
Cause : 50800028 (ExcCode 0a)^M
PrId : 0001992f (MIPS 1004Kc)^M
If I revert the patch then I can boot up again, all works as expected.
I am not exactly using a pure mainline 4.15 source base though.
(I have a bunch of additional changes to make this platform actually work).
But this patch certainly does trap as above when present. I am using
a gcc-5.4.0/binutils-2.25.1 toolchain.
Any thoughts?
Regards
Greg
> Fixes: 245a7868d2f2 ("MIPS: smp-cps: rework core/VPE initialisation")
> Signed-off-by: James Hogan <jhogan@xxxxxxxxxx>
> Cc: Paul Burton <paul.burton@xxxxxxxx>
> Cc: James Hogan <james.hogan@xxxxxxxx>
> Cc: James Hogan <jhogan@xxxxxxxxxx>
> Cc: Paul Burton <paul.burton@xxxxxxxx>
> Cc: linux-mips@xxxxxxxxxxxxxx
> Patchwork: https://patchwork.linux-mips.org/patch/17699/
> Signed-off-by: Ralf Baechle <ralf@xxxxxxxxxxxxxx>
> ---
> arch/mips/kernel/cps-vec.S | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
> index c7ed260..e68e6e0 100644
> --- a/arch/mips/kernel/cps-vec.S
> +++ b/arch/mips/kernel/cps-vec.S
> @@ -235,6 +235,7 @@ LEAF(mips_cps_core_init)
> has_mt t0, 3f
>
> .set push
> + .set MIPS_ISA_LEVEL_RAW
> .set mt
>
> /* Only allow 1 TC per VPE to execute... */
> @@ -388,6 +389,7 @@ LEAF(mips_cps_boot_vpes)
> #elif defined(CONFIG_MIPS_MT)
>
> .set push
> + .set MIPS_ISA_LEVEL_RAW
> .set mt
>
> /* If the core doesn't support MT then return */
> --
> 1.9.1
