On Fri, Jan 05, 2018 at 07:25:10PM +0100, Paul Cercueil wrote: > From: Maarten ter Huurne <maarten@xxxxxxxxxxxxxx> > > According to config2, the associativity would be 5-ways, but the > documentation states 4-ways, which also matches the documented > L2 cache size of 256 kB. > > Signed-off-by: Maarten ter Huurne <maarten@xxxxxxxxxxxxxx> Hehe, nice Reviewed-by: James Hogan <jhogan@xxxxxxxxxx> Cheers James > --- > arch/mips/mm/sc-mips.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > v2: No change > v3: No change > v4: Rebased on top of Linux 4.15-rc5 > v5: No change > v6: No change > > diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c > index 548acb7f8557..394673991bab 100644 > --- a/arch/mips/mm/sc-mips.c > +++ b/arch/mips/mm/sc-mips.c > @@ -16,6 +16,7 @@ > #include <asm/mmu_context.h> > #include <asm/r4kcache.h> > #include <asm/mips-cps.h> > +#include <asm/bootinfo.h> > > /* > * MIPS32/MIPS64 L2 cache handling > @@ -220,6 +221,14 @@ static inline int __init mips_sc_probe(void) > else > return 0; > > + /* > + * According to config2 it would be 5-ways, but that is contradicted > + * by all documentation. > + */ > + if (current_cpu_type() == CPU_JZRISC && > + mips_machtype == MACH_INGENIC_JZ4770) > + c->scache.ways = 4; > + > c->scache.waysize = c->scache.sets * c->scache.linesz; > c->scache.waybit = __ffs(c->scache.waysize); > > -- > 2.11.0 > >
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