This series enables the MIPS GIC driver to make use of the EIC mode
supported in some MIPS cores. In this mode, the cores 6 interrupt lines
are switched to represent a vector number, 0..63. Currently all GIC
interrupts are routed to a single CPU interrupt pin, but this is
inefficient since we end up checking both local and shared interrupt
flag registers for both local and shared interrupts. This introduces
additional latency into the interrupt paths. With EIC mode this can be
improved by using separate vectors for local and shared interrupts.
This series is based on 4.15-rc6 and has been tested on Boston, Malta &
SEAD3 MIPS platforms implementing a GIC with and without EIC mode
supported in hardware.
Matt Redfearn (6):
MIPS: Move ehb() to barrier.h
MIPS: CPS: Introduce mips_gic_enable_eic
MIPS: Generic: Support GIC in EIC mode
irqchip/mips-gic: Always attempt to enable EIC mode
irqchip/mips-gic: Use separate vector for shared interrupts in EIC
mode
irqchip/mips-gic: Separate local interrupt handling.
arch/mips/generic/irq.c | 18 +++++++++---------
arch/mips/include/asm/barrier.h | 13 +++++++++++++
arch/mips/include/asm/mips-gic.h | 22 ++++++++++++++++++++++
arch/mips/include/asm/mipsmtregs.h | 8 --------
drivers/irqchip/irq-mips-gic.c | 34 +++++++++++++++++++++++-----------
5 files changed, 67 insertions(+), 28 deletions(-)
--
2.7.4
