Hi Paul, > > Virtually all 64-bit MIPS processors have the CP0.Status.UX bit, which > > the Linux kernel keeps clear for o32 processes (CP0.Status.PX is currently > > unsupported and is kept clear as well), which means that an attempt to use > > any instruction that affects register bits beyond bit #31 will cause a > > Reserved Instruction exception, and in turn SIGILL being sent to the > > program. > > This isn't actually true - we currently set ST0_UX unconditionally if the > kernel is built with CONFIG_64BIT=y. It doesn't matter whether a user program > is MIPS32 or MIPS64 code, it always runs with UX=1. We also always save all 64 > bits of each GPR - not just the least significant 32 bits when running an o32 > program. I referred to plain 32-bit kernels (which I do acknowledge that I failed to communicate clearly, sorry), which is what we currently have under consideration (given the inability to support the generic case of an n64 binary with the address space limitation of the R5900 processor), and these do keep CP0.Status.UX clear and thus the rest of your observation is irrelevant (though it will be once we get to 64-bit support). One aspect of the limitation is the R5900 does not support the XTLB refill handler or the CP0 XContext register, so once we get to supporting 64-bit operation we'll have to maintain the TLB with the TLB refill handler and the CP0 Context register, which we currently don't with 64-bit kernels. Maciej
