Hello all,
On Tuesday, 5 September 2017 11:28:46 PDT Paul Burton wrote:
> The write_gic_smask() & write_gic_rmask() functions take a shared
> interrupt number as a parameter, but we're incorrectly providing them a
> bitmask with the shared interrupt's bit set. This effectively means that
> we mask or unmask the shared interrupt 1<<n rather than shared interrupt
> n, and as a result likely drop interrupts.
>
> Signed-off-by: Paul Burton <paul.burton@xxxxxxxxxx>
> Fixes: 68898c8765f4 ("irqchip: mips-gic: Drop gic_(re)set_mask() functions")
> Cc: Jason Cooper <jason@xxxxxxxxxxxxxx>
> Cc: Marc Zyngier <marc.zyngier@xxxxxxx>
> Cc: Ralf Baechle <ralf@xxxxxxxxxxxxxx>
> Cc: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
> Cc: linux-mips@xxxxxxxxxxxxxx
> ---
> With Boston PCIe support & the GIC cleanup series now coming together in
> -next, this bug was uncovered by running next-20170905 on a Boston
> board, which failed to find any rootfs media due to a lack of PCIe
> interrupts. With this fix we're now able to use the Boston's SATA or MMC
> controllers :)
>
> Ideally this would be applied as a fixup to 68898c8765f4 ("irqchip:
> mips-gic: Drop gic_(re)set_mask() functions"), but even if not it'd be
> great to get into the v4.14 MIPS pull where the breakage is introduced,
> or otherwise just ASAP - my apologies!
So this fix missed the MIPS pull - can we get it in ASAP, thorough either the
MIPS or irqchip trees?
Thanks,
Paul
> ---
> drivers/irqchip/irq-mips-gic.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
> index 6e52a88bbd9e..40159ac12ac8 100644
> --- a/drivers/irqchip/irq-mips-gic.c
> +++ b/drivers/irqchip/irq-mips-gic.c
> @@ -169,7 +169,7 @@ static void gic_mask_irq(struct irq_data *d)
> {
> unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);
>
> - write_gic_rmask(BIT(intr));
> + write_gic_rmask(intr);
> gic_clear_pcpu_masks(intr);
> }
>
> @@ -179,7 +179,7 @@ static void gic_unmask_irq(struct irq_data *d)
> unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);
> unsigned int cpu;
>
> - write_gic_smask(BIT(intr));
> + write_gic_smask(intr);
>
> gic_clear_pcpu_masks(intr);
> cpu = cpumask_first_and(affinity, cpu_online_mask);
> @@ -767,7 +767,7 @@ static int __init gic_of_init(struct device_node *node,
> for (i = 0; i < gic_shared_intrs; i++) {
> change_gic_pol(i, GIC_POL_ACTIVE_HIGH);
> change_gic_trig(i, GIC_TRIG_LEVEL);
> - write_gic_rmask(BIT(i));
> + write_gic_rmask(i);
> }
>
> for (i = 0; i < gic_vpes; i++) {
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