The MIPS timer, fast debug channel (FDC) & performance counter overflow
interrupts are all really percpu interrupts. However up until now the
users of these interrupt haven't used the percpu interrupt APIs to
configure & control them; instead using the regular non-percpu APIs such
as request_irq(), enable_irq() etc. This has required hacks elsewhere,
and generally does not fit well with the fact that the interrupts are
actually percpu.
The users of these interrupts are now prepared for them to be used with
the percpu interrupt APIs, so set them up as percpu_devid interrupts in
order to allow these users to begin using the percpu interrupt APIs.
Signed-off-by: Paul Burton <paul.burton@xxxxxxxxxx>
Cc: James Hogan <james.hogan@xxxxxxxxxx>
Cc: Jason Cooper <jason@xxxxxxxxxxxxxx>
Cc: Marc Zyngier <marc.zyngier@xxxxxxx>
Cc: Ralf Baechle <ralf@xxxxxxxxxxxxxx>
Cc: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
Cc: linux-kernel@xxxxxxxxxxxxxxx
Cc: linux-mips@xxxxxxxxxxxxxx
---
drivers/irqchip/irq-mips-cpu.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c
index 66f97fde13d8..8f7de01f6f35 100644
--- a/drivers/irqchip/irq-mips-cpu.c
+++ b/drivers/irqchip/irq-mips-cpu.c
@@ -166,7 +166,14 @@ static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq,
if (cpu_has_vint)
set_vi_handler(hw, plat_irq_dispatch);
- irq_set_chip_and_handler(irq, chip, handle_percpu_irq);
+ if ((irq == cp0_compare_irq) ||
+ (irq == cp0_fdc_irq) ||
+ (irq == cp0_perfcount_irq)) {
+ irq_set_chip_and_handler(irq, chip, handle_percpu_devid_irq);
+ irq_set_percpu_devid(irq);
+ } else {
+ irq_set_chip_and_handler(irq, chip, handle_percpu_irq);
+ }
return 0;
}
--
2.14.1
