This series includes a bunch of fixes & improvements for the MIPS SMP code, and in particular the MIPS Coherent Processing System (CPS) SMP implementation. Applies atop v4.12-rc3. Paul Burton (7): MIPS: Skip IPI setup if we only have 1 CPU MIPS: CM: Avoid per-core locking with CM3 & higher MIPS: CM: WARN on attempt to lock invalid VP, not BUG MIPS: CPS: Select CONFIG_SYS_SUPPORTS_SCHED_SMT for MIPSr6 MIPS: CPS: Prevent multi-core with dcache aliasing MIPS: CPS: Handle cores not powering down more gracefully MIPS: CPS: Handle spurious VP starts more gracefully arch/mips/Kconfig | 1 + arch/mips/kernel/cps-vec.S | 7 ++++++- arch/mips/kernel/mips-cm.c | 40 +++++++++++++++++++++++++++++++++------- arch/mips/kernel/smp-cps.c | 35 +++++++++++++++++++++++++++++------ arch/mips/kernel/smp.c | 3 +++ 5 files changed, 72 insertions(+), 14 deletions(-) -- 2.13.0
