On Mon, 27 Mar 2017, Joshua Kinard wrote: > > If you have any documentation to indicate a MIPS II CPU to support WAIT, > > I'm interested. From all that I know the feature was introduced by the > > R4600. > > One of my Google searches, using the keywords "mips wait instruction", has been > returning search results from a Harvard computer sciences course detailing the > "instructional operating system OS/161", which uses an instructional CPU that > borrows heavily from the R3000 (which they dub MIPS-161): > > http://os161.eecs.harvard.edu/documentation/sys161-1.99.07/mips.html > > In there, they state: > "The WAIT instruction has been borrowed from MIPS-II. This operation puts the > processor into a low-power state and suspends execution until some external > event occurs, such as an interrupt. Since the exact behavior of WAIT is not > clearly specified anywhere I could find, the MIPS-161 behavior is as follows" > > So it could be that the instructor for that course simply got some wrong > information, but good luck teaching Google that. I figure once its spider > crawls this e-mail in the archives, it'll further strengthen hits like the above. FWIW according to the MIPS IV ISA manual[1], which seems to be the most comprehensive legacy MIPS ISA instruction reference, COP0 encodings, and hence the WAIT instruction, have never been a part of any of the legacy MIPS ISAs, they have always been implementation-specific. Maciej References: [1] "MIPS IV Instruction Set", MIPS Technologies, Inc., Revision 3.2, By Charles Price, September, 1995, Section A 8.3.1 "Coprocessor 0 - COP0", p. A-176 <http://techpubs.sgi.com/library/manuals/2000/007-2597-001/pdf/007-2597-001.pdf>
