Some newer Loongson-3 has 64 bytes cache line size, so we select MIPS_L1_CACHE_SHIFT_6. Cc: stable@xxxxxxxxxxxxxxx Signed-off-by: Huacai Chen <chenhc@xxxxxxxxxx> --- arch/mips/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index e0bb576..c3c7d8a 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1373,6 +1373,7 @@ config CPU_LOONGSON3 select WEAK_ORDERING select WEAK_REORDERING_BEYOND_LLSC select MIPS_PGD_C0_CONTEXT + select MIPS_L1_CACHE_SHIFT_6 select GPIOLIB help The Loongson 3 processor implements the MIPS64R2 instruction -- 2.7.0
