Hi Steven,
On Thursday, 23 February 2017 13:49:54 PST Steven J. Hill wrote:
> From: "Steven J. Hill" <Steven.Hill@xxxxxxxxxx>
>
> * Remove unused header files and sort them by filename.
> * Convert 'union cvmx_pcie_address' to a bitfield.
It's already a bitfield - this patch is about making that bitfield endian-
safe, right? That seems to be the only significant change here so I'd suggest
changing the commit subject & message to reflect that.
> * Update copyright date.
I really don't see the point of mentioning trivia like that when you could
instead describe what your use of the __BITFIELD_FIELD macro is for (ie.
endianness).
Additionally it looks like this & your other patch "MIPS: Octeon: Enable PCIe
for little endian" probably ought to be a series, I imagine with this one
coming first.
Thanks,
Paul
>
> Signed-off-by: Steven J. Hill <steven.hill@xxxxxxxxxx>
> Signed-off-by: David Daney <david.daney@xxxxxxxxxx>
> ---
> arch/mips/pci/pcie-octeon.c | 84
> ++++++++++++++++++++++++--------------------- 1 file changed, 44
> insertions(+), 40 deletions(-)
>
> diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c
> index 9f672ce..8f267bf 100644
> --- a/arch/mips/pci/pcie-octeon.c
> +++ b/arch/mips/pci/pcie-octeon.c
> @@ -3,27 +3,24 @@
> * License. See the file "COPYING" in the main directory of this archive
> * for more details.
> *
> - * Copyright (C) 2007, 2008, 2009, 2010, 2011 Cavium Networks
> + * Copyright (C) 2007, 2008, 2009, 2010, 2017 Cavium Networks
> */
> -#include <linux/kernel.h>
> -#include <linux/init.h>
> #include <linux/pci.h>
> #include <linux/interrupt.h>
> -#include <linux/time.h>
> #include <linux/delay.h>
> #include <linux/moduleparam.h>
>
> #include <asm/octeon/octeon.h>
> +#include <asm/octeon/pci-octeon.h>
> +#include <asm/octeon/cvmx-dpi-defs.h>
> +#include <asm/octeon/cvmx-helper-errata.h>
> #include <asm/octeon/cvmx-npei-defs.h>
> #include <asm/octeon/cvmx-pciercx-defs.h>
> +#include <asm/octeon/cvmx-pemx-defs.h>
> #include <asm/octeon/cvmx-pescx-defs.h>
> #include <asm/octeon/cvmx-pexp-defs.h>
> -#include <asm/octeon/cvmx-pemx-defs.h>
> -#include <asm/octeon/cvmx-dpi-defs.h>
> #include <asm/octeon/cvmx-sli-defs.h>
> #include <asm/octeon/cvmx-sriox-defs.h>
> -#include <asm/octeon/cvmx-helper-errata.h>
> -#include <asm/octeon/pci-octeon.h>
>
> #define MRRS_CN5XXX 0 /* 128 byte Max Read Request Size */
> #define MPS_CN5XXX 0 /* 128 byte Max Packet Size (Limit of most PCs) */
> @@ -40,55 +37,62 @@
> union cvmx_pcie_address {
> uint64_t u64;
> struct {
> - uint64_t upper:2; /* Normally 2 for XKPHYS */
> - uint64_t reserved_49_61:13; /* Must be zero */
> - uint64_t io:1; /* 1 for IO space access */
> - uint64_t did:5; /* PCIe DID = 3 */
> - uint64_t subdid:3; /* PCIe SubDID = 1 */
> - uint64_t reserved_36_39:4; /* Must be zero */
> - uint64_t es:2; /* Endian swap = 1 */
> - uint64_t port:2; /* PCIe port 0,1 */
> - uint64_t reserved_29_31:3; /* Must be zero */
> + __BITFIELD_FIELD(uint64_t upper:2, /* Normally 2 for XKPHYS */
> + __BITFIELD_FIELD(uint64_t reserved_49_61:13, /* Must be zero */
> + __BITFIELD_FIELD(uint64_t io:1, /* 1 for IO space access */
> + __BITFIELD_FIELD(uint64_t did:5, /* PCIe DID = 3 */
> + __BITFIELD_FIELD(uint64_t subdid:3, /* PCIe SubDID = 1 */
> + __BITFIELD_FIELD(uint64_t reserved_36_39:4, /* Must be zero */
> + __BITFIELD_FIELD(uint64_t es:2, /* Endian swap = 1 */
> + __BITFIELD_FIELD(uint64_t port:2, /* PCIe port 0,1 */
> + __BITFIELD_FIELD(uint64_t reserved_29_31:3, /* Must be zero */
> /*
> * Selects the type of the configuration request (0 = type 0,
> * 1 = type 1).
> */
> - uint64_t ty:1;
> - /* Target bus number sent in the ID in the request. */
> - uint64_t bus:8;
> + __BITFIELD_FIELD(uint64_t ty:1,
> + /*
> + * Target bus number sent in the ID in the request.
> + */
> + __BITFIELD_FIELD(uint64_t bus:8,
> /*
> * Target device number sent in the ID in the
> * request. Note that Dev must be zero for type 0
> * configuration requests.
> */
> - uint64_t dev:5;
> - /* Target function number sent in the ID in the request. */
> - uint64_t func:3;
> + __BITFIELD_FIELD(uint64_t dev:5,
> + /*
> + * Target function number sent in the ID in the request.
> + */
> + __BITFIELD_FIELD(uint64_t func:3,
> /*
> * Selects a register in the configuration space of
> * the target.
> */
> - uint64_t reg:12;
> + __BITFIELD_FIELD(uint64_t reg:12,
> + ;))))))))))))))
> } config;
> struct {
> - uint64_t upper:2; /* Normally 2 for XKPHYS */
> - uint64_t reserved_49_61:13; /* Must be zero */
> - uint64_t io:1; /* 1 for IO space access */
> - uint64_t did:5; /* PCIe DID = 3 */
> - uint64_t subdid:3; /* PCIe SubDID = 2 */
> - uint64_t reserved_36_39:4; /* Must be zero */
> - uint64_t es:2; /* Endian swap = 1 */
> - uint64_t port:2; /* PCIe port 0,1 */
> - uint64_t address:32; /* PCIe IO address */
> + __BITFIELD_FIELD(uint64_t upper:2, /* Normally 2 for XKPHYS */
> + __BITFIELD_FIELD(uint64_t reserved_49_61:13, /* Must be zero */
> + __BITFIELD_FIELD(uint64_t io:1, /* 1 for IO space access */
> + __BITFIELD_FIELD(uint64_t did:5, /* PCIe DID = 3 */
> + __BITFIELD_FIELD(uint64_t subdid:3, /* PCIe SubDID = 2 */
> + __BITFIELD_FIELD(uint64_t reserved_36_39:4, /* Must be zero */
> + __BITFIELD_FIELD(uint64_t es:2, /* Endian swap = 1 */
> + __BITFIELD_FIELD(uint64_t port:2, /* PCIe port 0,1 */
> + __BITFIELD_FIELD(uint64_t address:32, /* PCIe IO address */
> + ;)))))))))
> } io;
> struct {
> - uint64_t upper:2; /* Normally 2 for XKPHYS */
> - uint64_t reserved_49_61:13; /* Must be zero */
> - uint64_t io:1; /* 1 for IO space access */
> - uint64_t did:5; /* PCIe DID = 3 */
> - uint64_t subdid:3; /* PCIe SubDID = 3-6 */
> - uint64_t reserved_36_39:4; /* Must be zero */
> - uint64_t address:36; /* PCIe Mem address */
> + __BITFIELD_FIELD(uint64_t upper:2, /* Normally 2 for XKPHYS */
> + __BITFIELD_FIELD(uint64_t reserved_49_61:13, /* Must be zero */
> + __BITFIELD_FIELD(uint64_t io:1, /* 1 for IO space access */
> + __BITFIELD_FIELD(uint64_t did:5, /* PCIe DID = 3 */
> + __BITFIELD_FIELD(uint64_t subdid:3, /* PCIe SubDID = 3-6 */
> + __BITFIELD_FIELD(uint64_t reserved_36_39:4, /* Must be zero */
> + __BITFIELD_FIELD(uint64_t address:36, /* PCIe Mem address */
> + ;)))))))
> } mem;
> };
Attachment:
signature.asc
Description: This is a digitally signed message part.
