From: "Steven J. Hill" <Steven.Hill@xxxxxxxxxx> Enable PCIe to work seamlessly for both endians. Signed-off-by: Steven J. Hill <steven.hill@xxxxxxxxxx> Signed-off-by: David Daney <david.daney@xxxxxxxxxx> --- arch/mips/pci/pcie-octeon.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c index 8f267bf..3c5419e 100644 --- a/arch/mips/pci/pcie-octeon.c +++ b/arch/mips/pci/pcie-octeon.c @@ -31,6 +31,13 @@ static int pcie_disable; module_param(pcie_disable, int, S_IRUGO); +/* Endian swap mode. */ +#ifdef __BIG_ENDIAN +#define _CVMX_PCIE_ES 1 +#else +#define _CVMX_PCIE_ES 0 +#endif + static int enable_pcie_14459_war; static int enable_pcie_bus_num_war[2]; @@ -116,7 +123,7 @@ static inline uint64_t cvmx_pcie_get_io_base_address(int pcie_port) pcie_addr.io.io = 1; pcie_addr.io.did = 3; pcie_addr.io.subdid = 2; - pcie_addr.io.es = 1; + pcie_addr.io.es = _CVMX_PCIE_ES; pcie_addr.io.port = pcie_port; return pcie_addr.u64; } @@ -247,7 +254,7 @@ static inline uint64_t __cvmx_pcie_build_config_addr(int pcie_port, int bus, pcie_addr.config.io = 1; pcie_addr.config.did = 3; pcie_addr.config.subdid = 1; - pcie_addr.config.es = 1; + pcie_addr.config.es = _CVMX_PCIE_ES; pcie_addr.config.port = pcie_port; pcie_addr.config.ty = (bus > pciercx_cfg006.s.pbnum); pcie_addr.config.bus = bus; @@ -1347,8 +1354,8 @@ static int __cvmx_pcie_rc_initialize_gen2(int pcie_port) mem_access_subid.u64 = 0; mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */ mem_access_subid.s.nmerge = 0; /* Allow merging as it works on CN6XXX. */ - mem_access_subid.s.esr = 1; /* Endian-swap for Reads. */ - mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */ + mem_access_subid.s.esr = _CVMX_PCIE_ES; /* Endian-swap for Reads. */ + mem_access_subid.s.esw = _CVMX_PCIE_ES; /* Endian-swap for Writes. */ mem_access_subid.s.wtype = 0; /* "No snoop" and "Relaxed ordering" are not set */ mem_access_subid.s.rtype = 0; /* "No snoop" and "Relaxed ordering" are not set */ /* PCIe Adddress Bits <63:34>. */ @@ -1398,7 +1405,7 @@ static int __cvmx_pcie_rc_initialize_gen2(int pcie_port) pemx_bar_ctl.u64 = cvmx_read_csr(CVMX_PEMX_BAR_CTL(pcie_port)); pemx_bar_ctl.s.bar1_siz = 3; /* 256MB BAR1*/ pemx_bar_ctl.s.bar2_enb = 1; - pemx_bar_ctl.s.bar2_esx = 1; + pemx_bar_ctl.s.bar2_esx = _CVMX_PCIE_ES; pemx_bar_ctl.s.bar2_cax = 0; cvmx_write_csr(CVMX_PEMX_BAR_CTL(pcie_port), pemx_bar_ctl.u64); sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(pcie_port)); -- 1.9.1
