On 02/10/2017 03:01 PM, James Hogan wrote:
The recently added MIPS cacheinfo support used a macro populate_cache()
to populate the cacheinfo structures depending on which caches are
present. However the macro contains multiple statements without
enclosing them in a do {} while (0) loop, so the L2 and L3 cache
conditionals in populate_cache_leaves() only conditionalised the first
statement in the macro.
This overflows the buffer allocated by detect_cache_attributes(),
resulting in boot failures under QEMU where neither the L2 or L2 caches
are present.
Enclose the macro statements in a do {} while (0) block to keep the
whole macro inside the conditionals.
Fixes: ef462f3b64e9 ("MIPS: Add cacheinfo support")
Reported-by: Guenter Roeck <linux@xxxxxxxxxxxx>
Signed-off-by: James Hogan <james.hogan@xxxxxxxxxx>
Tested-by: Guenter Roeck <linux@xxxxxxxxxxxx>
Cc: Ralf Baechle <ralf@xxxxxxxxxxxxxx>
Cc: Justin Chen <justin.chen@xxxxxxxxxxxx>
Cc: Florian Fainelli <f.fainelli@xxxxxxxxx>
Cc: linux-mips@xxxxxxxxxxxxxx
Cc: bcm-kernel-feedback-list@xxxxxxxxxxxx
---
arch/mips/kernel/cacheinfo.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/mips/kernel/cacheinfo.c b/arch/mips/kernel/cacheinfo.c
index a92bbbae969b..97d5239ca47b 100644
--- a/arch/mips/kernel/cacheinfo.c
+++ b/arch/mips/kernel/cacheinfo.c
@@ -17,6 +17,7 @@
/* Populates leaf and increments to next leaf */
#define populate_cache(cache, leaf, c_level, c_type) \
+do { \
leaf->type = c_type; \
leaf->level = c_level; \
leaf->coherency_line_size = c->cache.linesz; \
@@ -24,7 +25,8 @@
leaf->ways_of_associativity = c->cache.ways; \
leaf->size = c->cache.linesz * c->cache.sets * \
c->cache.ways; \
- leaf++;
+ leaf++; \
+} while (0)
static int __init_cache_level(unsigned int cpu)
{
