Re: [PATCH v4 1/8] MIPS: Loongson: Merge RPID macro for Loongson-1A/1B/1C

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To: Binbin Zhou <zhoubb@xxxxxxxxxx>, Ralf Baechle <ralf@xxxxxxxxxxxxxx>
Subject: Re: [PATCH v4 1/8] MIPS: Loongson: Merge RPID macro for Loongson-1A/1B/1C
From: Sergei Shtylyov <sergei.shtylyov@xxxxxxxxxxxxxxxxxx>
Date: Tue, 7 Feb 2017 12:26:20 +0300
Cc: John Crispin <john@xxxxxxxxxxx>, "Steven J . Hill" <Steven.Hill@xxxxxxxxxx>, linux-mips@xxxxxxxxxxxxxx, Fuxin Zhang <zhangfx@xxxxxxxxxx>, Zhangjin Wu <wuzhangjin@xxxxxxxxx>, Kelvin Cheung <keguang.zhang@xxxxxxxxx>, Yang Ling <gnaygnil@xxxxxxxxx>, HuaCai Chen <chenhc@xxxxxxxxxx>
In-reply-to: <1486452550-10721-2-git-send-email-zhoubb@lemote.com>
References: <1486452550-10721-1-git-send-email-zhoubb@lemote.com> <1486452550-10721-2-git-send-email-zhoubb@lemote.com>
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Hello!

On 2/7/2017 10:29 AM, Binbin Zhou wrote:

The Loongson-1 series CPUs(1A/1B/1C) share the same RPID macro.


   Maybe PRID?

Signed-off-by: Binbin Zhou <zhoubb@xxxxxxxxxx>
Signed-off-by: HuaCai Chen <chenhc@xxxxxxxxxx>

[...]

MBR, Sergei

References:
- [PATCH v4 0/8] MIPS: Loongson: Add the Loongson-1A processor support
  - From: Binbin Zhou
- [PATCH v4 1/8] MIPS: Loongson: Merge RPID macro for Loongson-1A/1B/1C
  - From: Binbin Zhou

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