From: Joshua Kinard <kumba@xxxxxxxxxx> Add a new header 'pcibr.h' to arch/mips/include/asm/mach-ip27 which contains IP27-specific definitions for the BRIDGE ASIC used to connect PCI devices to the Crosstalk bus. Signed-off-by: Joshua Kinard <kumba@xxxxxxxxxx> --- arch/mips/include/asm/mach-ip27/pcibr.h | 50 +++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/mips/include/asm/mach-ip27/pcibr.h b/arch/mips/include/asm/mach-ip27/pcibr.h new file mode 100644 index 000000000000..6664843c30f9 --- /dev/null +++ b/arch/mips/include/asm/mach-ip27/pcibr.h @@ -0,0 +1,50 @@ +/* + * Definitions for PCI bridges in IP27. Derived from pcibr.h in the + * IP30 port. + * + * Copyright (C) 2004-2007 Stanislaw Skowronek <skylark@xxxxxxxxxxxxx> + * Copyright (C) 2015-2016 Joshua Kinard <kumba@xxxxxxxxxx> + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#ifndef __ASM_MACH_IP27_PCIBR_H +#define __ASM_MACH_IP27_PCIBR_H + +#include <asm/pci/bridge.h> +#include <asm/mach-ip27/irq.h> + +/* Xtalk */ +#define PCIBR_OFFSET_MEM 0x200000 +#define PCIBR_OFFSET_IO 0xa00000 +#define PCIBR_OFFSET_END 0xc00000 + +/* + * This is how XIO sees HUB's PI_INT_PEND_MOD register. + */ +#define PCIBR_XIO_SEES_HUB 0x01800090 + +/* + * Max # of PCI buses we can handle; ie, max #PCI bridges. + */ +#define PCIBR_MAX_NUM_PCIBUS 40 + +/* + * Max # of PCI devices (like scsi controllers) we handle on a bus. + */ +#define PCIBR_MAX_DEV_PCIBUS 8 + +/* + * Used by ip27-bridge.c and ip27-irq.c. + */ +#define PCIBR_MAX_BUS_X_DEV (PCIBR_MAX_NUM_PCIBUS * PCIBR_MAX_DEV_PCIBUS) +extern struct bridge_controller *irq_to_bridge[PCIBR_MAX_BUS_X_DEV]; +extern u32 irq_to_slot[PCIBR_MAX_BUS_X_DEV]; + +/* XXX: Temporary until IP27 "mega update". */ +extern int request_bridge_irq(struct bridge_controller *bc); + +#endif /* __ASM_MACH_IP27_PCIBR_H */ + -- 2.11.1
