On Thu, Dec 08, 2016 at 05:01:53PM -0800, Leonid Yegoshin wrote: > CACHE instruction is not available in user space, only SYNCI on MIPS R2+ for > trampoline. > Any operation with CACHE requires a syscall. Even worse, some older CPUs allow the execution of certain CACHE operations from user space. This is a feature which can be disabled by kernel. > As for SYNCI (trampoline from L1D->L1I) the following information in user > space is needed: > > 1. L1 line size (available via RDHWR $x, $1). It is available now > directly from CPU, but may be better to supply from kernel because some > cores has no that. > > 2. The flag that L1I is NOT coherent with L1D and SYNCI is needed and > available > > The knowledge about L1/L2 sizes is not needed for regular application... > well, if application wants to get advantage of cache sizes, well, in this > case it can be supplied. > > But it is unreliable because app may be rescheduled into different kind of > core which has a different L1 size (in heterogeneous system, BTW). It can be > fixed by setting affinity, of course (not sure - can it be reliably done in > BIG/LITTLE approach). But that requires in application the knowledge and > understanding of system CPU structure... well why we can allow all that > stuff besides information purpose? It corrupts the all efforts and > optimization in kernel about performance and powersaving. Also let's not forget about CPUs like Octeons which have CPUs that don't quite fit in the usual scheme of doing things. Ralf
