Le 25/11/2016 à 10:46, Paul Burton a écrit : > The behaviour of mips_dma_unmap_page() & mips_dma_unmap_sg() with > regards to cache maintenance differ for no good reason. Whilst > mips_dma_unmap_page() correctly takes into account whether a CPU may > have speculatively prefetched data into caches by using > cpu_needs_post_dma_flush(), it ignores the direction of the DMA transfer > & thus performs cache maintenance after DMA_TO_DEVICE transfers for no > good reason. Meanwhile mips_dma_unmap_sg() avoids unnecessary cache > maintenance for DMA_TO_DEVICE transfers but performs unnecessary cache > maintenance on CPUs which cannot have speculatively fetched data into > the caches. > > Fix this by using the same condition for cache maintenance in both > mips_dma_unmap_page() & mips_dma_unmap_sg(). We perform cache > maintenance when unmapping if and only if both: > > - cpu_needs_post_dma_flush() returns true, indicating that the device > performing DMA is not cache-coherent and the CPU may speculatively > prefetch data from memory being DMAed to. > > - The direction of the DMA is not DMA_TO_DEVICE, meaning that the > device may have written to memory & we should invalidate our cached > view in order to observe whatever the device wrote. > > Signed-off-by: Paul Burton <paul.burton@xxxxxxxxxx> > Cc: Ralf Baechle <ralf@xxxxxxxxxxxxxx> > Cc: linux-mips@xxxxxxxxxxxxxx Reviewed-by: Florian Fainelli <f.fainelli@xxxxxxxxx> -- Florian
