The manual states "A 74K processor contains no direct hardware support for managing coherency with respect to its caches, so it must be handled via the system design or software" Signed-off-by: Sven Schnelle <svens@xxxxxxxxxxxxxx> --- arch/mips/mm/dma-default.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index 46d5696..575b7b8 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -73,7 +73,8 @@ static inline int cpu_needs_post_dma_flush(struct device *dev) return !plat_device_is_coherent(dev) && (boot_cpu_type() == CPU_R10000 || boot_cpu_type() == CPU_R12000 || - boot_cpu_type() == CPU_BMIPS5000); + boot_cpu_type() == CPU_BMIPS5000 || + boot_cpu_type() == CPU_74K); } static gfp_t massage_gfp_flags(const struct device *dev, gfp_t gfp) -- 2.10.2
