tree: git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill.git mips-for-linux-next
head: 2b7731edf0eed4ca80d5c9b28d6976876d4513fc
commit: 2c4664fee89b173c12bb6282b7d86153ae26b0d4 [12/100] MIPS: Loongson1C: Add board support
config: mips-loongson1c_defconfig (attached as .config)
compiler: mipsel-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout 2c4664fee89b173c12bb6282b7d86153ae26b0d4
# save the attached .config to linux build tree
make.cross ARCH=mips
All errors (new ones prefixed by >>):
drivers/clk/clk-ls1x.c: In function 'ls1x_clk_init':
>> drivers/clk/clk-ls1x.c:114:11: error: 'BYPASS_CPU_SHIFT' undeclared (first use in this function)
BYPASS_CPU_SHIFT, BYPASS_CPU_WIDTH, 0, &_lock);
^~~~~~~~~~~~~~~~
drivers/clk/clk-ls1x.c:114:11: note: each undeclared identifier is reported only once for each function it appears in
>> drivers/clk/clk-ls1x.c:114:29: error: 'BYPASS_CPU_WIDTH' undeclared (first use in this function)
BYPASS_CPU_SHIFT, BYPASS_CPU_WIDTH, 0, &_lock);
^~~~~~~~~~~~~~~~
>> drivers/clk/clk-ls1x.c:130:11: error: 'BYPASS_DC_SHIFT' undeclared (first use in this function)
BYPASS_DC_SHIFT, BYPASS_DC_WIDTH, 0, &_lock);
^~~~~~~~~~~~~~~
>> drivers/clk/clk-ls1x.c:130:28: error: 'BYPASS_DC_WIDTH' undeclared (first use in this function)
BYPASS_DC_SHIFT, BYPASS_DC_WIDTH, 0, &_lock);
^~~~~~~~~~~~~~~
>> drivers/clk/clk-ls1x.c:147:11: error: 'BYPASS_DDR_SHIFT' undeclared (first use in this function)
BYPASS_DDR_SHIFT, BYPASS_DDR_WIDTH, 0, &_lock);
^~~~~~~~~~~~~~~~
>> drivers/clk/clk-ls1x.c:147:29: error: 'BYPASS_DDR_WIDTH' undeclared (first use in this function)
BYPASS_DDR_SHIFT, BYPASS_DDR_WIDTH, 0, &_lock);
^~~~~~~~~~~~~~~~
vim +/BYPASS_CPU_WIDTH +114 drivers/clk/clk-ls1x.c
3526f74f Kelvin Cheung 2014-10-10 108 CLK_DIVIDER_ONE_BASED |
3526f74f Kelvin Cheung 2014-10-10 109 CLK_DIVIDER_ROUND_CLOSEST, &_lock);
3526f74f Kelvin Cheung 2014-10-10 110 clk_register_clkdev(clk, "cpu_clk_div", NULL);
3526f74f Kelvin Cheung 2014-10-10 111 clk = clk_register_mux(NULL, "cpu_clk", cpu_parents,
3526f74f Kelvin Cheung 2014-10-10 112 ARRAY_SIZE(cpu_parents),
3526f74f Kelvin Cheung 2014-10-10 113 CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,
3526f74f Kelvin Cheung 2014-10-10 @114 BYPASS_CPU_SHIFT, BYPASS_CPU_WIDTH, 0, &_lock);
3526f74f Kelvin Cheung 2014-10-10 115 clk_register_clkdev(clk, "cpu_clk", NULL);
3526f74f Kelvin Cheung 2014-10-10 116
3526f74f Kelvin Cheung 2014-10-10 117 /* _____
3526f74f Kelvin Cheung 2014-10-10 118 * _______________________| |
3526f74f Kelvin Cheung 2014-10-10 119 * OSC ___/ | MUX |___ DC CLK
3526f74f Kelvin Cheung 2014-10-10 120 * \___ PLL ___ DC DIV ___| |
3526f74f Kelvin Cheung 2014-10-10 121 * |_____|
3526f74f Kelvin Cheung 2014-10-10 122 */
3526f74f Kelvin Cheung 2014-10-10 123 clk = clk_register_divider(NULL, "dc_clk_div", "pll_clk",
3526f74f Kelvin Cheung 2014-10-10 124 0, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
5175cb58 Kelvin Cheung 2012-08-20 125 DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
3526f74f Kelvin Cheung 2014-10-10 126 clk_register_clkdev(clk, "dc_clk_div", NULL);
3526f74f Kelvin Cheung 2014-10-10 127 clk = clk_register_mux(NULL, "dc_clk", dc_parents,
3526f74f Kelvin Cheung 2014-10-10 128 ARRAY_SIZE(dc_parents),
3526f74f Kelvin Cheung 2014-10-10 129 CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,
3526f74f Kelvin Cheung 2014-10-10 @130 BYPASS_DC_SHIFT, BYPASS_DC_WIDTH, 0, &_lock);
3526f74f Kelvin Cheung 2014-10-10 131 clk_register_clkdev(clk, "dc_clk", NULL);
3526f74f Kelvin Cheung 2014-10-10 132
3526f74f Kelvin Cheung 2014-10-10 133 /* _____
3526f74f Kelvin Cheung 2014-10-10 134 * _______________________| |
3526f74f Kelvin Cheung 2014-10-10 135 * OSC ___/ | MUX |___ DDR CLK
3526f74f Kelvin Cheung 2014-10-10 136 * \___ PLL ___ DDR DIV ___| |
3526f74f Kelvin Cheung 2014-10-10 137 * |_____|
3526f74f Kelvin Cheung 2014-10-10 138 */
3526f74f Kelvin Cheung 2014-10-10 139 clk = clk_register_divider(NULL, "ahb_clk_div", "pll_clk",
3526f74f Kelvin Cheung 2014-10-10 140 0, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT,
3526f74f Kelvin Cheung 2014-10-10 141 DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED,
3526f74f Kelvin Cheung 2014-10-10 142 &_lock);
3526f74f Kelvin Cheung 2014-10-10 143 clk_register_clkdev(clk, "ahb_clk_div", NULL);
3526f74f Kelvin Cheung 2014-10-10 144 clk = clk_register_mux(NULL, "ahb_clk", ahb_parents,
3526f74f Kelvin Cheung 2014-10-10 145 ARRAY_SIZE(ahb_parents),
3526f74f Kelvin Cheung 2014-10-10 146 CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,
3526f74f Kelvin Cheung 2014-10-10 @147 BYPASS_DDR_SHIFT, BYPASS_DDR_WIDTH, 0, &_lock);
3526f74f Kelvin Cheung 2014-10-10 148 clk_register_clkdev(clk, "ahb_clk", NULL);
5175cb58 Kelvin Cheung 2012-08-20 149 clk_register_clkdev(clk, "stmmaceth", NULL);
5175cb58 Kelvin Cheung 2012-08-20 150
:::::: The code at line 114 was first introduced by commit
:::::: 3526f74fa925e44335b94ed0c9f93648e26058ef clk: ls1x: Update relationship among all clocks
:::::: TO: Kelvin Cheung <keguang.zhang@xxxxxxxxx>
:::::: CC: Ralf Baechle <ralf@xxxxxxxxxxxxxx>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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