The L1 data cache in I6400 CPUs is indexed by physical address bits if
an entry for the address is present in the DTLB early enough in the
pipelined execution of a memory access instruction. If an entry is not
present then it's indexed by virtual address bits, but hardware will
check in a later pipeline stage when a DTLB entry has been created
whether the virtual address bits used match the physical address bits,
and if not will transparently restart the memory access instruction.
This means that although it isn't always physically indexed, it appears
so to software & we can treat the I6400 L1 data cache as being
physically indexed in order to avoid considering aliasing.
Signed-off-by: Paul Burton <paul.burton@xxxxxxxxxx>
---
arch/mips/mm/c-r4k.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index ef7f925..7a64a8a81 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1266,6 +1266,7 @@ static void probe_pcache(void)
switch (current_cpu_type()) {
case CPU_20KC:
case CPU_25KF:
+ case CPU_I6400:
case CPU_SB1:
case CPU_SB1A:
case CPU_XLR:
@@ -1292,7 +1293,6 @@ static void probe_pcache(void)
case CPU_PROAPTIV:
case CPU_M5150:
case CPU_QEMU_GENERIC:
- case CPU_I6400:
case CPU_P6600:
case CPU_M6250:
if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
--
2.9.3
