This is a set of patches to add 48-bit virtual address space support on MIPS to the kernel 3.10. It includes a port of existing patch for page size 16k and 64k, plus support for 4-level page table for the rest of the supported page sizes. Cc: David Saney <ddaney@xxxxxxxxxxxxxxxxxx> Cc: Ralf Baechle <ralf@xxxxxxxxxxxxxx> Cc: linux-mips@xxxxxxxxxxxxxx Signed-off-by: Alex Belits <alex.belits@xxxxxxxxxx> --- arch/mips/include/asm/pgtable-64.h | 14 +++++++------- arch/mips/include/asm/processor.h | 2 +- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h index a86bb73..e9805ad 100644 --- a/arch/mips/include/asm/pgtable-64.h +++ b/arch/mips/include/asm/pgtable-64.h @@ -45,7 +45,7 @@ /* PGDIR_SHIFT determines what a third-level page table entry can map */ #ifdef __PAGETABLE_PMD_FOLDED -#define PGDIR_SHIFT (PAGE_SHIFT + PAGE_SHIFT + PTE_ORDER - 3) +#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 3)) #else /* PMD_SHIFT determines the size of the area a second-level page table can map */ @@ -60,7 +60,7 @@ #define PGDIR_MASK (~(PGDIR_SIZE-1)) /* - * For 4kB page size we use a 3 level page tree and an 8kB pud, which + * For 4kB page size we use a 3 level page tree and an 8kB pgd, which * permits us mapping 40 bits of virtual address space. * * We used to implement 41 bits by having an order 1 pmd level but that seemed @@ -70,8 +70,8 @@ * 8TB of address space. Alternatively a 33-bit / 8GB organization using * two levels would be easy to implement. * - * For 16kB page size we use a 2 level page tree which permits a total of - * 36 bits of virtual address space. We could add a third level but it seems + * For 16kB page size we use a 3 level page tree which permits a total of + * 47 bits of virtual address space. We could add a third level but it seems * like at the moment there's no need for this. * * For 64kB page size we use a 2 level page table tree for a total of 42 bits @@ -91,9 +91,9 @@ #endif #ifdef CONFIG_PAGE_SIZE_16KB #ifdef CONFIG_MIPS_VA_BITS_48 -#define PGD_ORDER 1 +#define PGD_ORDER 1 #else -#define PGD_ORDER 0 +#define PGD_ORDER 0 #endif #define PUD_ORDER aieeee_attempt_to_allocate_pud #define PMD_ORDER 0 @@ -122,7 +122,7 @@ #endif #define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t)) -#define USER_PTRS_PER_PGD ((TASK_SIZE64 / PGDIR_SIZE)?(TASK_SIZE64 / PGDIR_SIZE):1) +#define USER_PTRS_PER_PGD ((TASK_SIZE64 / PGDIR_SIZE) ? (TASK_SIZE64 / PGDIR_SIZE) : 1) #define FIRST_USER_ADDRESS 0UL /* diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index fc1c0af..083a56f 100644 --- a/arch/mips/include/asm/processor.h +++ b/arch/mips/include/asm/processor.h @@ -72,7 +72,7 @@ extern unsigned int vced_count, vcei_count; */ #define TASK_SIZE32 0x7fff8000UL #ifdef CONFIG_MIPS_VA_BITS_48 -#define TASK_SIZE64 (0x1UL << ((cpu_data[0].vmbits>48)?48:cpu_data[0].vmbits)) +#define TASK_SIZE64 (0x1UL << ((cpu_data[0].vmbits > 48) ? 48 : cpu_data[0].vmbits)) #else #define TASK_SIZE64 0x10000000000UL #endif -- 2.8.1
