On 11/08/16 11:34, Matt Redfearn wrote:
>>> - gic_send_ipi(intr);
>>> -
>>> - if (mips_cpc_present() && (core != current_cpu_data.core)) {
>>> - while (!cpumask_test_cpu(cpu, &cpu_coherent_mask)) {
>>> - mips_cm_lock_other(core, 0);
>>> - mips_cpc_lock_other(core);
>>> - write_cpc_co_cmd(CPC_Cx_CMD_PWRUP);
>>> - mips_cpc_unlock_other();
>>> - mips_cm_unlock_other();
>>> - }
>>> - }
>> Hi Matt,
>>
>> This patch itself makes sense, but it does bring to light that the IPI
>> IRQ domain stuff will have broken cpuidle. When a core goes into one of
>> the deeper power saving states (becoming clock gated or power gated) it
>> won't automatically wake back up upon interrupts, which is why the bit
>> of code above exists to bring it back out of the power saving state via
>> the CPC.
>
> There is equivalent code to that removed by the IPI IRQ domain here:
> http://lxr.free-electrons.com/source/arch/mips/kernel/smp.c#L185.
>
> With a 2c2t Interaptiv, core 1 does seem to be getting clock & power gated:
> # cat /sys/devices/system/cpu/cpu2/cpuidle/state2/desc
> core clock gated
> # cat /sys/devices/system/cpu/cpu2/cpuidle/state3/desc
> core power gated
> # cat /sys/devices/system/cpu/cpu2/cpuidle/state2/time
> 7007
> # cat /sys/devices/system/cpu/cpu2/cpuidle/state3/time
> 300549307
> # cat /sys/devices/system/cpu/cpu3/cpuidle/state2/time
> 8556
> # cat /sys/devices/system/cpu/cpu3/cpuidle/state3/time
> 301527771
>
> So I think it's all good.
Hi Matt,
Right you are :) I hadn't realised the code had been copied there.
Thanks,
Paul
